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-rw-r--r--src/arch/x86/isa/operands.isa6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 25b73a8f2..51b9b73a6 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -97,7 +97,11 @@ def operands {{
'FpSrcReg2': floatReg('src2', 21),
'FpDestReg': floatReg('dest', 22),
'FpData': floatReg('data', 23),
- 'PCS': ('PCState', 'udw', None,
+ 'RIP': ('PCState', 'uqw', 'pc',
+ (None, None, 'IsControl'), 50),
+ 'NRIP': ('PCState', 'uqw', 'npc',
+ (None, None, 'IsControl'), 50),
+ 'nuIP': ('PCState', 'uqw', 'nupc',
(None, None, 'IsControl'), 50),
# This holds the condition code portion of the flag register. The
# nccFlagBits version holds the rest.