diff options
Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index e0ace11d0..8e2ae7fd4 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -119,10 +119,13 @@ def operands {{ # This holds the condition code portion of the flag register. The # nccFlagBits version holds the rest. 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), + 'cfofBits': intReg('INTREG_PSEUDO(1)', 61), + 'ecfBit': intReg('INTREG_PSEUDO(2)', 62), + 'ezfBit': intReg('INTREG_PSEUDO(3)', 63), # These register should needs to be more protected so that later # instructions don't map their indexes with an old value. - 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61), - 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'), + 'nccFlagBits': controlReg('MISCREG_RFLAGS', 64), + 'TOP': controlReg('MISCREG_X87_TOP', 65, ctype='ub'), # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |