diff options
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 5 | ||||
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 6bd26608e..35f319528 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1100,6 +1100,11 @@ let {{ DestReg = TscOp; ''' + class Rdm5reg(RdRegOp): + code = ''' + DestReg = M5Reg; + ''' + class Wrdl(RegOp): code = ''' SegDescriptor desc = SrcReg1; diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index f002b2cea..446580c1b 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -151,5 +151,6 @@ def operands {{ 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207), 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208), 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209), + 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 210), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300) }}; |