diff options
Diffstat (limited to 'src/arch/x86/isa')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/isa/formats/unknown.isa | 4 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 13 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/seqop.isa | 16 | ||||
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 5 |
5 files changed, 27 insertions, 13 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index de167d1c1..def9b7f9d 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -199,7 +199,7 @@ #endif 0x54: m5panic({{ panic("M5 panic instruction called at pc=%#x.\n", - xc->readPC()); + xc->pcState().pc()); }}, IsNonSpeculative); 0x55: m5reserved1({{ warn("M5 reserved opcode 1 ignored.\n"); diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa index 11751e861..1108fd4a4 100644 --- a/src/arch/x86/isa/formats/unknown.isa +++ b/src/arch/x86/isa/formats/unknown.isa @@ -47,13 +47,13 @@ output header {{ /** * Class for Unknown/Illegal instructions */ - class Unknown : public StaticInst + class Unknown : public X86ISA::X86StaticInst { public: // Constructor Unknown(ExtMachInst _machInst) : - StaticInst("unknown", _machInst, No_OpClass) + X86ISA::X86StaticInst("unknown", _machInst, No_OpClass) { } diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 9ccea82dd..86ebac174 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -944,8 +944,12 @@ let {{ code = 'DoubleBits = psrc1 ^ op2;' class Wrip(WrRegOp, CondRegOp): - code = 'RIP = psrc1 + sop2 + CSBase' - else_code="RIP = RIP;" + code = ''' + X86ISA::PCState pc = PCS; + pc.npc(psrc1 + sop2 + CSBase); + PCS = pc; + ''' + else_code = "PCS = PCS;" class Wruflags(WrRegOp): code = 'ccFlagBits = psrc1 ^ op2' @@ -961,7 +965,10 @@ let {{ ''' class Rdip(RdRegOp): - code = 'DestReg = RIP - CSBase' + code = ''' + X86ISA::PCState pc = PCS; + DestReg = pc.npc() - CSBase; + ''' class Ruflags(RdRegOp): code = 'DestReg = ccFlagBits' diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa index 57c44d48c..a3e22b0aa 100644 --- a/src/arch/x86/isa/microops/seqop.isa +++ b/src/arch/x86/isa/microops/seqop.isa @@ -169,15 +169,23 @@ let {{ return super(Eret, self).getAllocator(microFlags) iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase", - {"code": "nuIP = target", - "else_code": "nuIP = nuIP", + {"code": ''' + X86ISA::PCState pc = PCS; + pc.nupc(target); + PCS = pc; + ''', + "else_code": "PCS = PCS", "cond_test": "checkCondition(ccFlagBits, cc)"}) exec_output += SeqOpExecute.subst(iop) header_output += SeqOpDeclare.subst(iop) decoder_output += SeqOpConstructor.subst(iop) iop = InstObjParams("br", "MicroBranch", "SeqOpBase", - {"code": "nuIP = target", - "else_code": "nuIP = nuIP", + {"code": ''' + X86ISA::PCState pc = PCS; + pc.nupc(target); + PCS = pc; + ''', + "else_code": "PCS = PCS", "cond_test": "true"}) exec_output += SeqOpExecute.subst(iop) header_output += SeqOpDeclare.subst(iop) diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index d4140e414..25b73a8f2 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -97,9 +97,8 @@ def operands {{ 'FpSrcReg2': floatReg('src2', 21), 'FpDestReg': floatReg('dest', 22), 'FpData': floatReg('data', 23), - 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), - 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), - 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), + 'PCS': ('PCState', 'udw', None, + (None, None, 'IsControl'), 50), # This holds the condition code portion of the flag register. The # nccFlagBits version holds the rest. 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), |