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-rw-r--r--src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
index 2bb3e7a42..1017d519f 100644
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
@@ -105,7 +105,7 @@ fxsave32Template = """
rdval t1, "InstRegIndex(MISCREG_FOSEG)"
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2
-"""
+""" + fxsaveCommonTemplate
fxsave64Template = """
rdval t1, "InstRegIndex(MISCREG_FIOFF)"
@@ -113,7 +113,7 @@ fxsave64Template = """
rdval t1, "InstRegIndex(MISCREG_FOOFF)"
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8
-"""
+""" + fxsaveCommonTemplate
fxrstorCommonTemplate = """
ld t1, seg, %(mode)s, "DISPLACEMENT + 0", dataSize=2
@@ -149,7 +149,7 @@ fxrstor32Template = """
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2
wrval "InstRegIndex(MISCREG_FOSEG)", t1
-"""
+""" + fxrstorCommonTemplate
fxrstor64Template = """
limm t2, 0, dataSize=8
@@ -161,7 +161,7 @@ fxrstor64Template = """
ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8
wrval "InstRegIndex(MISCREG_FOOFF)", t1
wrval "InstRegIndex(MISCREG_FOSEG)", t2
-"""
+""" + fxrstorCommonTemplate
microcode = '''
def macroop FXSAVE_M {