diff options
Diffstat (limited to 'src/arch/x86/isa')
22 files changed, 240 insertions, 154 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index ecb92947f..f76912f06 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -302,7 +302,7 @@ } 0x12: decode OPCODE_OP_BOTTOM3 { 0x0: Inst::NOP(); //XXX repe makes this a "pause" - default: xchg_B_rAX(); + default: Inst::XCHG(Bv,rAv); } 0x13: decode OPCODE_OP_BOTTOM3 { 0x0: Inst::CDQE(rAv); @@ -330,20 +330,20 @@ 0x1: mov_rAX_Ov(); 0x2: mov_Ob_Al(); 0x3: mov_Ov_rAX(); - 0x4: movs_Yb_Xb(); - 0x5: movs_Yv_Xv(); - 0x6: StringInst::CMPS(Yb,Xb); - 0x7: StringInst::CMPS(Yv,Xv); + 0x4: StringInst::MOVS(Yb,Xb); + 0x5: StringInst::MOVS(Yv,Xv); + 0x6: StringTestInst::CMPS(Yb,Xb); + 0x7: StringTestInst::CMPS(Yv,Xv); } 0x15: decode OPCODE_OP_BOTTOM3 { 0x0: Inst::TEST(rAb,Ib); 0x1: Inst::TEST(rAv,Iz); - 0x2: stos_Yb_Al(); - 0x3: stos_Yv_rAX(); + 0x2: StringInst::STOS(Yb); + 0x3: StringInst::STOS(Yv); 0x4: lods_Al_Xb(); 0x5: lods_rAX_Xv(); - 0x6: StringInst::SCAS(Yb); - 0x7: StringInst::SCAS(Yv); + 0x6: StringTestInst::SCAS(Yb); + 0x7: StringTestInst::SCAS(Yv); } format Inst { 0x16: MOV(Bb,Ib); diff --git a/src/arch/x86/isa/formats/string.isa b/src/arch/x86/isa/formats/string.isa index cd182ff62..b1d3c4bbe 100644 --- a/src/arch/x86/isa/formats/string.isa +++ b/src/arch/x86/isa/formats/string.isa @@ -61,7 +61,7 @@ // ////////////////////////////////////////////////////////////////////////// -def format StringInst(*opTypeSet) {{ +def format StringTestInst(*opTypeSet) {{ allBlocks = OutputBlocks() regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv()) @@ -86,3 +86,29 @@ def format StringInst(*opTypeSet) {{ (header_output, decoder_output, decode_block, exec_output) = allBlocks.makeList() }}; + +def format StringInst(*opTypeSet) {{ + allBlocks = OutputBlocks() + + regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv()) + eBlocks = specializeInst(Name + "_E", list(opTypeSet), EmulEnv()) + + for blocks in (regBlocks, eBlocks): + allBlocks.header_output += blocks.header_output + allBlocks.decoder_output += blocks.decoder_output + allBlocks.exec_output += blocks.exec_output + + allBlocks.decode_block = ''' + if (LEGACY_REP) { + %s + } else if (LEGACY_REPNE) { + // The repne prefix is illegal + return new MicroFault(machInst, "illprefix", new InvalidOpcode); + } else { + %s + } + ''' % (eBlocks.decode_block, regBlocks.decode_block) + + (header_output, decoder_output, + decode_block, exec_output) = allBlocks.makeList() +}}; diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 0679e972b..6724ea9b0 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -145,6 +145,7 @@ output exec {{ #include <cmath> #include "arch/x86/miscregs.hh" +#include "arch/x86/tlb.hh" #include "base/bigint.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py index 87fbb796c..e58fc00d7 100644 --- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py @@ -68,7 +68,7 @@ def macroop ADD_R_I def macroop ADD_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -77,14 +77,14 @@ def macroop ADD_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop ADD_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -92,7 +92,7 @@ def macroop ADD_M_R def macroop ADD_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -137,7 +137,7 @@ def macroop SUB_R_P def macroop SUB_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -146,14 +146,14 @@ def macroop SUB_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop SUB_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -161,7 +161,7 @@ def macroop SUB_M_R def macroop SUB_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -180,7 +180,7 @@ def macroop ADC_R_I def macroop ADC_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -189,14 +189,14 @@ def macroop ADC_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop ADC_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -204,7 +204,7 @@ def macroop ADC_M_R def macroop ADC_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -249,7 +249,7 @@ def macroop SBB_R_P def macroop SBB_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -258,14 +258,14 @@ def macroop SBB_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop SBB_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -273,7 +273,7 @@ def macroop SBB_M_R def macroop SBB_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -285,7 +285,7 @@ def macroop NEG_R def macroop NEG_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) st t1, seg, sib, disp }; @@ -293,7 +293,7 @@ def macroop NEG_M def macroop NEG_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py index 2a8024eee..7afd24992 100644 --- a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py @@ -61,7 +61,7 @@ def macroop INC_R def macroop INC_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, sib, disp }; @@ -69,7 +69,7 @@ def macroop INC_M def macroop INC_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, riprel, disp }; @@ -81,7 +81,7 @@ def macroop DEC_R def macroop DEC_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, sib, disp }; @@ -89,7 +89,7 @@ def macroop DEC_M def macroop DEC_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py index 504e9ab0a..f4f856974 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py @@ -61,8 +61,9 @@ def macroop CALL_NEAR_I limm t1, imm rdip t7 + # Check target of call + st t7, ss, [0, t0, rsp], "-env.dataSize" subi rsp, rsp, dsz - st t7, ss, [0, t0, rsp] wrip t7, t1 }; @@ -72,8 +73,9 @@ def macroop CALL_NEAR_R .adjust_env oszIn64Override rdip t1 + # Check target of call + st t1, ss, [0, t0, rsp], "-env.dataSize" subi rsp, rsp, dsz - st t1, ss, [0, t0, rsp] wripi reg, 0 }; @@ -84,8 +86,9 @@ def macroop CALL_NEAR_M rdip t7 ld t1, seg, sib, disp + # Check target of call + st t7, ss, [0, t0, rsp], "-env.dataSize" subi rsp, rsp, dsz - st t7, ss, [0, t0, rsp] wripi t1, 0 }; @@ -96,8 +99,9 @@ def macroop CALL_NEAR_P rdip t7 ld t1, seg, riprel, disp + # Check target of call + st t7, ss, [0, t0, rsp], "-env.dataSize" subi rsp, rsp, dsz - st t7, ss, [0, t0, rsp] wripi t1, 0 }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py index 1efddf1d2..8993f5ac4 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py @@ -60,6 +60,7 @@ def macroop RET_NEAR .adjust_env oszIn64Override ld t1, ss, [1, t0, rsp] + # Check address of return addi rsp, rsp, dsz wripi t1, 0 }; @@ -71,6 +72,7 @@ def macroop RET_NEAR_I limm t2, imm ld t1, ss, [1, t0, rsp] + # Check address of return addi rsp, rsp, dsz add rsp, rsp, t2 wripi t1, 0 diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py index 9e6807039..5fb2b2172 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py @@ -67,6 +67,7 @@ def macroop POP_M { .adjust_env oszIn64Override ld t1, ss, [1, t0, rsp] + # Check stack address addi rsp, rsp, dsz st t1, seg, sib, disp }; @@ -77,6 +78,7 @@ def macroop POP_P { rdip t7 ld t1, ss, [1, t0, rsp] + # Check stack address addi rsp, rsp, dsz st t1, seg, riprel, disp }; @@ -96,8 +98,8 @@ def macroop PUSH_I { .adjust_env oszIn64Override limm t1, imm + st t1, ss, [1, t0, rsp], "-env.dataSize" subi rsp, rsp, dsz - st t1, ss, [1, t0, rsp] }; def macroop PUSH_M { @@ -105,8 +107,8 @@ def macroop PUSH_M { .adjust_env oszIn64Override ld t1, seg, sib, disp + st t1, ss, [1, t0, rsp], "-env.dataSize" subi rsp, rsp, dsz - st t1, ss, [1, t0, rsp] }; def macroop PUSH_P { @@ -115,11 +117,13 @@ def macroop PUSH_P { rdip t7 ld t1, seg, riprel, disp + # Check stack address subi rsp, rsp, dsz st t1, ss, [1, t0, rsp] }; def macroop PUSHA { + # Check all the stack addresses. st rax, ss, [1, t0, rsp], "-0 * env.dataSize" st rcx, ss, [1, t0, rsp], "-1 * env.dataSize" st rdx, ss, [1, t0, rsp], "-2 * env.dataSize" @@ -132,6 +136,7 @@ def macroop PUSHA { }; def macroop POPA { + # Check all the stack addresses. ld rdi, ss, [1, t0, rsp], "0 * env.dataSize" ld rsi, ss, [1, t0, rsp], "1 * env.dataSize" ld rbp, ss, [1, t0, rsp], "2 * env.dataSize" @@ -146,8 +151,9 @@ def macroop LEAVE { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - mov rsp, rsp, rbp - ld rbp, ss, [1, t0, rsp] + mov t1, t1, rbp + ld rbp, ss, [1, t0, t1] + mov rsp, rsp, t1 addi rsp, rsp, dsz }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py index 9478c71fc..3f243f5d8 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py @@ -68,7 +68,7 @@ def macroop XCHG_R_R def macroop XCHG_R_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp st reg, seg, sib, disp mov reg, reg, t1 }; @@ -76,14 +76,14 @@ def macroop XCHG_R_M def macroop XCHG_R_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp st reg, seg, riprel, disp mov reg, reg, t1 }; def macroop XCHG_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp st reg, seg, sib, disp mov reg, reg, t1 }; @@ -91,7 +91,7 @@ def macroop XCHG_M_R def macroop XCHG_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp st reg, seg, riprel, disp mov reg, reg, t1 }; diff --git a/src/arch/x86/isa/insts/general_purpose/logical.py b/src/arch/x86/isa/insts/general_purpose/logical.py index 2137ae82f..a8b7c6a45 100644 --- a/src/arch/x86/isa/insts/general_purpose/logical.py +++ b/src/arch/x86/isa/insts/general_purpose/logical.py @@ -62,7 +62,7 @@ def macroop OR_R_R def macroop OR_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -71,14 +71,14 @@ def macroop OR_P_I { limm t2, imm rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; def macroop OR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -86,7 +86,7 @@ def macroop OR_M_R def macroop OR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; @@ -124,7 +124,7 @@ def macroop XOR_R_I def macroop XOR_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -133,14 +133,14 @@ def macroop XOR_P_I { limm t2, imm rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; def macroop XOR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -148,7 +148,7 @@ def macroop XOR_M_R def macroop XOR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; @@ -192,7 +192,7 @@ def macroop AND_R_I def macroop AND_M_I { - ld t2, seg, sib, disp + ldst t2, seg, sib, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) st t2, seg, sib, disp @@ -201,7 +201,7 @@ def macroop AND_M_I def macroop AND_P_I { rdip t7 - ld t2, seg, riprel, disp + ldst t2, seg, riprel, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) st t2, seg, riprel, disp @@ -209,7 +209,7 @@ def macroop AND_P_I def macroop AND_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -217,7 +217,7 @@ def macroop AND_M_R def macroop AND_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; @@ -231,7 +231,7 @@ def macroop NOT_R def macroop NOT_M { limm t1, -1 - ld t2, seg, sib, disp + ldst t2, seg, sib, disp xor t2, t2, t1 st t2, seg, sib, disp }; @@ -240,7 +240,7 @@ def macroop NOT_P { limm t1, -1 rdip t7 - ld t2, seg, riprel, disp + ldst t2, seg, riprel, disp xor t2, t2, t1 st t2, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py index a13df3a64..b5ae9560e 100644 --- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py @@ -61,7 +61,7 @@ def macroop ROL_R_I def macroop ROL_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp roli t1, t1, imm st t1, seg, sib, disp }; @@ -69,7 +69,7 @@ def macroop ROL_M_I def macroop ROL_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp roli t1, t1, imm st t1, seg, riprel, disp }; @@ -81,7 +81,7 @@ def macroop ROL_1_R def macroop ROL_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp roli t1, t1, 1 st t1, seg, sib, disp }; @@ -89,7 +89,7 @@ def macroop ROL_1_M def macroop ROL_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp roli t1, t1, 1 st t1, seg, riprel, disp }; @@ -101,7 +101,7 @@ def macroop ROL_R_R def macroop ROL_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rol t1, t1, reg st t1, seg, sib, disp }; @@ -109,7 +109,7 @@ def macroop ROL_M_R def macroop ROL_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rol t1, t1, reg st t1, seg, riprel, disp }; @@ -121,7 +121,7 @@ def macroop ROR_R_I def macroop ROR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rori t1, t1, imm st t1, seg, sib, disp }; @@ -129,7 +129,7 @@ def macroop ROR_M_I def macroop ROR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rori t1, t1, imm st t1, seg, riprel, disp }; @@ -141,7 +141,7 @@ def macroop ROR_1_R def macroop ROR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rori t1, t1, 1 st t1, seg, sib, disp }; @@ -149,7 +149,7 @@ def macroop ROR_1_M def macroop ROR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rori t1, t1, 1 st t1, seg, riprel, disp }; @@ -161,7 +161,7 @@ def macroop ROR_R_R def macroop ROR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp ror t1, t1, reg st t1, seg, sib, disp }; @@ -169,7 +169,7 @@ def macroop ROR_M_R def macroop ROR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp ror t1, t1, reg st t1, seg, riprel, disp }; @@ -181,7 +181,7 @@ def macroop RCL_R_I def macroop RCL_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcli t1, t1, imm st t1, seg, sib, disp }; @@ -189,7 +189,7 @@ def macroop RCL_M_I def macroop RCL_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcli t1, t1, imm st t1, seg, riprel, disp }; @@ -201,7 +201,7 @@ def macroop RCL_1_R def macroop RCL_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcli t1, t1, 1 st t1, seg, sib, disp }; @@ -209,7 +209,7 @@ def macroop RCL_1_M def macroop RCL_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcli t1, t1, 1 st t1, seg, riprel, disp }; @@ -221,7 +221,7 @@ def macroop RCL_R_R def macroop RCL_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcl t1, t1, reg st t1, seg, sib, disp }; @@ -229,7 +229,7 @@ def macroop RCL_M_R def macroop RCL_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcl t1, t1, reg st t1, seg, riprel, disp }; @@ -241,7 +241,7 @@ def macroop RCR_R_I def macroop RCR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcri t1, t1, imm st t1, seg, sib, disp }; @@ -249,7 +249,7 @@ def macroop RCR_M_I def macroop RCR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcri t1, t1, imm st t1, seg, riprel, disp }; @@ -261,7 +261,7 @@ def macroop RCR_1_R def macroop RCR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcri t1, t1, 1 st t1, seg, sib, disp }; @@ -269,7 +269,7 @@ def macroop RCR_1_M def macroop RCR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcri t1, t1, 1 st t1, seg, riprel, disp }; @@ -281,7 +281,7 @@ def macroop RCR_R_R def macroop RCR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcr t1, t1, reg st t1, seg, sib, disp }; @@ -289,7 +289,7 @@ def macroop RCR_M_R def macroop RCR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcr t1, t1, reg st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py index 6c688cca3..ed7d761b8 100644 --- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py @@ -61,7 +61,7 @@ def macroop SAL_R_I def macroop SAL_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp slli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -69,7 +69,7 @@ def macroop SAL_M_I def macroop SAL_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp slli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -81,7 +81,7 @@ def macroop SAL_1_R def macroop SAL_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp slli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -89,7 +89,7 @@ def macroop SAL_1_M def macroop SAL_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp slli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -101,7 +101,7 @@ def macroop SAL_R_R def macroop SAL_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sll t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -109,7 +109,7 @@ def macroop SAL_M_R def macroop SAL_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sll t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -121,7 +121,7 @@ def macroop SHR_R_I def macroop SHR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -129,7 +129,7 @@ def macroop SHR_M_I def macroop SHR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -141,7 +141,7 @@ def macroop SHR_1_R def macroop SHR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -149,7 +149,7 @@ def macroop SHR_1_M def macroop SHR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -161,7 +161,7 @@ def macroop SHR_R_R def macroop SHR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srl t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -169,7 +169,7 @@ def macroop SHR_M_R def macroop SHR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srl t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -181,7 +181,7 @@ def macroop SAR_R_I def macroop SAR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srai t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -189,7 +189,7 @@ def macroop SAR_M_I def macroop SAR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srai t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -201,7 +201,7 @@ def macroop SAR_1_R def macroop SAR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srai t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -209,7 +209,7 @@ def macroop SAR_1_M def macroop SAR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srai t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -221,7 +221,7 @@ def macroop SAR_R_R def macroop SAR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sra t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -229,7 +229,7 @@ def macroop SAR_M_R def macroop SAR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sra t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py index 800f1b325..27a31dbd9 100644 --- a/src/arch/x86/isa/insts/general_purpose/semaphores.py +++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py @@ -61,7 +61,7 @@ def macroop CMPXCHG_R_R { }; def macroop CMPXCHG_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) @@ -71,7 +71,7 @@ def macroop CMPXCHG_M_R { def macroop CMPXCHG_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) diff --git a/src/arch/x86/isa/insts/general_purpose/string/move_string.py b/src/arch/x86/isa/insts/general_purpose/string/move_string.py index 0a855b384..b64acfdc2 100644 --- a/src/arch/x86/isa/insts/general_purpose/string/move_string.py +++ b/src/arch/x86/isa/insts/general_purpose/string/move_string.py @@ -53,16 +53,36 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class MOVS(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSB(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSW(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSD(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSQ(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop MOVS_M_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + ld t1, seg, [1, t0, rsi] + st t1, es, [1, t0, rdi] + + add rdi, rdi, t3, dataSize=asz + add rsi, rsi, t3, dataSize=asz +}; + +def macroop MOVS_E_M_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + +topOfLoop: + ld t1, seg, [1, t0, rsi] + st t1, es, [1, t0, rdi] + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t3, dataSize=asz + add rsi, rsi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; +''' diff --git a/src/arch/x86/isa/insts/general_purpose/string/store_string.py b/src/arch/x86/isa/insts/general_purpose/string/store_string.py index 08a126c1f..a8d558929 100644 --- a/src/arch/x86/isa/insts/general_purpose/string/store_string.py +++ b/src/arch/x86/isa/insts/general_purpose/string/store_string.py @@ -53,16 +53,32 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class STOS(Inst): -# "Add 0 0 0" -# class STOSB(Inst): -# "Add 0 0 0" -# class STOSW(Inst): -# "Add 0 0 0" -# class STOSD(Inst): -# "Add 0 0 0" -# class STOSQ(Inst): -# "Add 0 0 0" -#}}; +microcode = ''' +def macroop STOS_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + st rax, es, [1, t0, rdi] + + add rdi, rdi, t3, dataSize=asz +}; + +def macroop STOS_E_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + +topOfLoop: + st rax, es, [1, t0, rdi] + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py index de89005f2..76279fc70 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py @@ -55,30 +55,35 @@ microcode = ''' def macroop MOVAPS_R_M { + # Check low address. ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8 ldfp xmml, seg, sib, disp, dataSize=8 }; def macroop MOVAPS_R_P { rdip t7 + # Check low address. ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8 ldfp xmml, seg, riprel, disp, dataSize=8 }; def macroop MOVAPS_M_R { + # Check low address. stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8 stfp xmml, seg, sib, disp, dataSize=8 }; def macroop MOVAPS_P_R { rdip t7 + # Check low address. stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8 stfp xmml, seg, riprel, disp, dataSize=8 }; def macroop MOVAPS_R_R { - movfp xmml, xmml, xmmlm, dataSize=8 - movfp xmmh, xmmh, xmmhm, dataSize=8 + # Check low address. + movfp xmml, xmmlm, dataSize=8 + movfp xmmh, xmmhm, dataSize=8 }; # MOVAPD @@ -107,7 +112,7 @@ def macroop MOVLPD_P_R { }; def macroop MOVLPD_R_R { - movfp xmml, xmml, xmmlm, dataSize=8 + movfp xmml, xmmlm, dataSize=8 }; # MOVHLPS @@ -135,6 +140,6 @@ def macroop MOVSD_P_R { }; def macroop MOVSD_R_R { - movfp xmml, xmml, xmmlm, dataSize=8 + movfp xmml, xmmlm, dataSize=8 }; ''' diff --git a/src/arch/x86/isa/insts/system/undefined_operation.py b/src/arch/x86/isa/insts/system/undefined_operation.py index e5544b6e7..9f129522b 100644 --- a/src/arch/x86/isa/insts/system/undefined_operation.py +++ b/src/arch/x86/isa/insts/system/undefined_operation.py @@ -56,6 +56,6 @@ microcode = ''' def macroop UD2 { - fault "new X86Fault" + fault "new InvalidOpcode()" }; ''' diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py index 37574da34..2a4c3f0ed 100644 --- a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py @@ -56,33 +56,31 @@ microcode = ''' def macroop FLD_M { ldfp ufp1, seg, sib, disp - movfp st(1), ufp1, spm=-1 + movfp st(-1), ufp1, spm=-1 }; def macroop FLD_P { rdip t7 ldfp ufp1, seg, riprel, disp - movfp st(1), ufp1, spm=-1 + movfp st(-1), ufp1, spm=-1 }; def macroop FST_M { - movfp st(0), ufp1 - stfp ufp1, seg, sib, disp + stfp st(0), seg, sib, disp }; def macroop FST_P { - movfp st(0), ufp1 rdip t7 - stfp ufp1, seg, riprel, disp + stfp st(0), seg, riprel, disp }; def macroop FSTP_M { - movfp st(0), ufp1, spm=1 + movfp ufp1, st(0), spm=1 stfp ufp1, seg, sib, disp }; def macroop FSTP_P { - movfp st(0), ufp1, spm=1 + movfp ufp1, st(0), spm=1 rdip t7 stfp ufp1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index e961cc63c..c8bc36b69 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -137,7 +137,7 @@ let {{ assembler.symbols["label"] = labeler def stack_index(index): - return "(NUM_FLOATREGS + (%s))" % index + return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index assembler.symbols["st"] = stack_index diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index e9a7cb84f..2919aa277 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -260,7 +260,7 @@ let {{ SetStatus=False, dataSize="env.dataSize"): super(Movfp, self).__init__(dest, src1, flags, \ spm, SetStatus, dataSize) - code = 'FpDestReg.uqw = FpSrcReg2.uqw;' + code = 'FpDestReg.uqw = FpSrcReg1.uqw;' else_code = 'FpDestReg.uqw = FpDestReg.uqw;' cond_check = "checkCondition(ccFlagBits, src2)" diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 1bdc1d37a..106a8a0fe 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -123,7 +123,7 @@ def template MicroLoadExecute {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - fault = read(xc, EA, Mem, 0); + fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment)); if(fault == NoFault) { @@ -150,7 +150,7 @@ def template MicroLoadInitiateAcc {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - fault = read(xc, EA, Mem, 0); + fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment)); return fault; } @@ -197,7 +197,7 @@ def template MicroStoreExecute {{ if(fault == NoFault) { - fault = write(xc, Mem, EA, 0); + fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment)); if(fault == NoFault) { %(op_wb)s; @@ -224,7 +224,7 @@ def template MicroStoreInitiateAcc {{ if(fault == NoFault) { - fault = write(xc, Mem, EA, 0); + fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment)); if(fault == NoFault) { %(op_wb)s; @@ -358,7 +358,7 @@ let {{ calculateEA = "EA = SegBase + scale * Index + Base + disp;" - def defineMicroLoadOp(mnemonic, code): + def defineMicroLoadOp(mnemonic, code, mem_flags=0): global header_output global decoder_output global exec_output @@ -368,7 +368,9 @@ let {{ # Build up the all register version of this micro op iop = InstObjParams(name, Name, 'X86ISA::LdStOp', - {"code": code, "ea_code": calculateEA}) + {"code": code, + "ea_code": calculateEA, + "mem_flags": mem_flags}) header_output += MicroLdStOpDeclare.subst(iop) decoder_output += MicroLdStOpConstructor.subst(iop) exec_output += MicroLoadExecute.subst(iop) @@ -386,9 +388,10 @@ let {{ microopClasses[name] = LoadOp defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') + defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 'StoreCheck') defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') - def defineMicroStoreOp(mnemonic, code): + def defineMicroStoreOp(mnemonic, code, mem_flags=0): global header_output global decoder_output global exec_output @@ -398,7 +401,9 @@ let {{ # Build up the all register version of this micro op iop = InstObjParams(name, Name, 'X86ISA::LdStOp', - {"code": code, "ea_code": calculateEA}) + {"code": code, + "ea_code": calculateEA, + "mem_flags": mem_flags}) header_output += MicroLdStOpDeclare.subst(iop) decoder_output += MicroLdStOpConstructor.subst(iop) exec_output += MicroStoreExecute.subst(iop) @@ -419,7 +424,9 @@ let {{ defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', - {"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA}) + {"code": "Data = merge(Data, EA, dataSize);", + "ea_code": calculateEA, + "mem_flags": 0}) header_output += MicroLeaDeclare.subst(iop) decoder_output += MicroLdStOpConstructor.subst(iop) exec_output += MicroLeaExecute.subst(iop) diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 40a441b1e..de2e6692d 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -439,10 +439,11 @@ let {{ abstract = True flag_code = ''' //Don't have genFlags handle the OF or CF bits - uint64_t mask = CFBit | OFBit; + uint64_t mask = CFBit | ECFBit | OFBit; ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); //If a logic microop wants to set these, it wants to set them to 0. ccFlagBits &= ~(CFBit & ext); + ccFlagBits &= ~(ECFBit & ext); ccFlagBits &= ~(OFBit & ext); ''' @@ -852,7 +853,7 @@ let {{ class Ruflag(RegOp): code = ''' - int flag = bits(ccFlagBits, imm8 + 0*psrc1); + int flag = bits(ccFlagBits, imm8); DestReg = merge(DestReg, flag, dataSize); ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); |