diff options
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r-- | src/arch/x86/isa/decoder/one_byte_opcodes.isa | 40 | ||||
-rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 | ||||
-rw-r--r-- | src/arch/x86/isa/formats/basic.isa | 9 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 10 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/general_purpose/string/load_string.py | 42 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/system/__init__.py | 3 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 74 | ||||
-rw-r--r-- | src/arch/x86/isa/microasm.isa | 4 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 22 | ||||
-rw-r--r-- | src/arch/x86/isa/specialize.isa | 3 |
10 files changed, 155 insertions, 56 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index f76912f06..da7867401 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -325,27 +325,27 @@ default: lahf(); } } - 0x14: decode OPCODE_OP_BOTTOM3 { - 0x0: mov_Al_Ob(); - 0x1: mov_rAX_Ov(); - 0x2: mov_Ob_Al(); - 0x3: mov_Ov_rAX(); - 0x4: StringInst::MOVS(Yb,Xb); - 0x5: StringInst::MOVS(Yv,Xv); - 0x6: StringTestInst::CMPS(Yb,Xb); - 0x7: StringTestInst::CMPS(Yv,Xv); - } - 0x15: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::TEST(rAb,Ib); - 0x1: Inst::TEST(rAv,Iz); - 0x2: StringInst::STOS(Yb); - 0x3: StringInst::STOS(Yv); - 0x4: lods_Al_Xb(); - 0x5: lods_rAX_Xv(); - 0x6: StringTestInst::SCAS(Yb); - 0x7: StringTestInst::SCAS(Yv); - } format Inst { + 0x14: decode OPCODE_OP_BOTTOM3 { + 0x0: MOV(rAb, Ob); + 0x1: MOV(rAv, Ov); + 0x2: MOV(Ob, rAb); + 0x3: MOV(Ov, rAv); + 0x4: StringInst::MOVS(Yb,Xb); + 0x5: StringInst::MOVS(Yv,Xv); + 0x6: StringTestInst::CMPS(Yb,Xb); + 0x7: StringTestInst::CMPS(Yv,Xv); + } + 0x15: decode OPCODE_OP_BOTTOM3 { + 0x0: TEST(rAb,Ib); + 0x1: TEST(rAv,Iz); + 0x2: StringInst::STOS(Yb); + 0x3: StringInst::STOS(Yv); + 0x4: StringInst::LODS(Xb); + 0x5: StringInst::LODS(Xv); + 0x6: StringTestInst::SCAS(Yb); + 0x7: StringTestInst::SCAS(Yv); + } 0x16: MOV(Bb,Ib); 0x17: MOV(Bv,Iv); 0x18: decode OPCODE_OP_BOTTOM3 { diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index eae994706..0482fdf23 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -211,9 +211,9 @@ default: Inst::UD2(); } 0x06: decode OPCODE_OP_BOTTOM3 { - 0x0: wrmsr(); + 0x0: Inst::WRMSR(); 0x1: rdtsc(); - 0x2: rdmsr(); + 0x2: Inst::RDMSR(); 0x3: rdpmc(); 0x4: sysenter(); 0x5: sysexit(); diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa index ea224d638..7aea7085f 100644 --- a/src/arch/x86/isa/formats/basic.isa +++ b/src/arch/x86/isa/formats/basic.isa @@ -147,12 +147,3 @@ def template BasicDecode {{ def template BasicDecodeWithMnemonic {{ return new %(class_name)s("%(mnemonic)s", machInst); }}; - -// The most basic instruction format... used only for a few misc. insts -def format BasicOperate(code, *flags) {{ - iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py index a248f5656..04f9ea12a 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py @@ -59,6 +59,16 @@ microcode = ''' # Regular moves # +def macroop MOV_R_MI { + limm t1, imm + ld reg, seg, [1, t0, t1] +}; + +def macroop MOV_MI_R { + limm t1, imm + st reg, seg, [1, t0, t1] +}; + def macroop MOV_R_R { mov reg, reg, regm }; diff --git a/src/arch/x86/isa/insts/general_purpose/string/load_string.py b/src/arch/x86/isa/insts/general_purpose/string/load_string.py index 0f749a273..61525c2f2 100644 --- a/src/arch/x86/isa/insts/general_purpose/string/load_string.py +++ b/src/arch/x86/isa/insts/general_purpose/string/load_string.py @@ -53,16 +53,32 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class LODS(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSB(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSW(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSD(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSQ(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop LODS_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + ld rax, seg, [1, t0, rdi] + + add rdi, rdi, t3, dataSize=asz +}; + +def macroop LODS_E_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + +topOfLoop: + ld rax, seg, [1, t0, rdi] + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; +''' diff --git a/src/arch/x86/isa/insts/system/__init__.py b/src/arch/x86/isa/insts/system/__init__.py index 72e3bdf0a..6d4b3f3d1 100644 --- a/src/arch/x86/isa/insts/system/__init__.py +++ b/src/arch/x86/isa/insts/system/__init__.py @@ -53,7 +53,8 @@ # # Authors: Gabe Black -categories = ["undefined_operation"] +categories = ["undefined_operation", + "msrs"] microcode = "" for category in categories: diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py new file mode 100644 index 000000000..ea576510b --- /dev/null +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -0,0 +1,74 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop WRMSR +{ + limm t1, "IntAddrPrefixMSR >> 3" + ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4 + mov rax, rax, t2, dataSize=4 + srli t2, t2, 32, dataSize=8 + mov rdx, rdx, t2, dataSize=4 +}; + +def macroop RDMSR +{ + limm t1, "IntAddrPrefixMSR >> 3" + mov t2, t2, rdx, dataSize=4 + slli t2, t2, 32, dataSize=8 + mov t2, t2, rax, dataSize=4 + st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4 +}; +''' diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index c8bc36b69..50135e30c 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -106,6 +106,10 @@ let {{ assembler.symbols["riprel"] = \ ["1", assembler.symbols["t0"], assembler.symbols["t7"]] + # This segment selects an internal address space mapped to MSRs, + # CPUID info, etc. + assembler.symbols["intseg"] = "NUM_SEGMENTREGS" + for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 106a8a0fe..32fefb5fa 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -325,13 +325,13 @@ def template MicroLdStOpConstructor {{ let {{ class LdStOp(X86Microop): - def __init__(self, data, segment, addr, disp, dataSize): + def __init__(self, data, segment, addr, disp, dataSize, addressSize): self.data = data [self.scale, self.index, self.base] = addr self.disp = disp self.segment = segment self.dataSize = dataSize - self.addressSize = "env.addressSize" + self.addressSize = addressSize def getAllocator(self, *microFlags): allocator = '''new %(class_name)s(machInst, mnemonic @@ -378,10 +378,10 @@ let {{ exec_output += MicroLoadCompleteAcc.subst(iop) class LoadOp(LdStOp): - def __init__(self, data, segment, addr, - disp = 0, dataSize="env.dataSize"): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", addressSize="env.addressSize"): super(LoadOp, self).__init__(data, segment, - addr, disp, dataSize) + addr, disp, dataSize, addressSize) self.className = Name self.mnemonic = name @@ -411,10 +411,10 @@ let {{ exec_output += MicroStoreCompleteAcc.subst(iop) class StoreOp(LdStOp): - def __init__(self, data, segment, addr, - disp = 0, dataSize="env.dataSize"): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", addressSize="env.addressSize"): super(StoreOp, self).__init__(data, segment, - addr, disp, dataSize) + addr, disp, dataSize, addressSize) self.className = Name self.mnemonic = name @@ -432,10 +432,10 @@ let {{ exec_output += MicroLeaExecute.subst(iop) class LeaOp(LdStOp): - def __init__(self, data, segment, addr, - disp = 0, dataSize="env.dataSize"): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", addressSize="env.addressSize"): super(LeaOp, self).__init__(data, segment, - addr, disp, dataSize) + addr, disp, dataSize, addressSize) self.className = "Lea" self.mnemonic = "lea" diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index 59e9577d9..cf6b6ff86 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -172,6 +172,9 @@ let {{ elif opType.tag in ("I", "J"): # Immediates Name += "_I" + elif opType.tag == "O": + # Immediate containing a memory offset + Name += "_MI" elif opType.tag in ("PR", "R", "VR"): # Non register modrm settings should cause an error env.addReg(ModRMRMIndex) |