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-rw-r--r--src/arch/x86/isa/includes.isa5
-rw-r--r--src/arch/x86/isa/insts/arithmetic/add_and_subtract.py20
-rw-r--r--src/arch/x86/isa/insts/compare_and_test/test.py34
-rw-r--r--src/arch/x86/isa/insts/control_transfer/call.py13
-rw-r--r--src/arch/x86/isa/insts/data_transfer/move.py42
-rw-r--r--src/arch/x86/isa/insts/data_transfer/stack_operations.py14
-rw-r--r--src/arch/x86/isa/insts/load_effective_address.py6
-rw-r--r--src/arch/x86/isa/insts/logical.py62
-rw-r--r--src/arch/x86/isa/microasm.isa28
-rw-r--r--src/arch/x86/isa/microops/regop.isa64
10 files changed, 149 insertions, 139 deletions
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 14406931b..3ef204850 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -97,7 +97,6 @@ output header {{
#include <iostream>
#include "arch/x86/emulenv.hh"
-#include "arch/x86/faults.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/regfile.hh"
#include "arch/x86/types.hh"
@@ -105,10 +104,12 @@ output header {{
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh" // some constructors use MemReq flags
+#include "sim/faults.hh"
}};
output decoder {{
-
+#include "arch/x86/faults.hh"
+#include "arch/x86/segmentregs.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index de66f70f3..809b9ac7c 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -56,26 +56,22 @@
microcode = '''
def macroop SUB_R_I
{
- subi "env.reg", "env.reg", "IMMEDIATE"
+ subi reg, reg, imm
};
def macroop SUB_M_I
{
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- subi "NUM_INTREGS+1", "NUM_INTREGS+1", "IMMEDIATE"
- st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ ld t1, ds, [scale, index, base], disp
+ subi t1, t1, imm
+ st t1, ds, [scale, index, base], disp
};
def macroop SUB_P_I
{
- rdip "NUM_INTREGS+7"
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- subi "NUM_INTREGS+1", "NUM_INTREGS+1", "IMMEDIATE"
- st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ subi t1, t1, imm
+ st t1, ds, [scale, index, base], disp
};
'''
#let {{
diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py
index 7b4ab0781..89d406912 100644
--- a/src/arch/x86/isa/insts/compare_and_test/test.py
+++ b/src/arch/x86/isa/insts/compare_and_test/test.py
@@ -56,44 +56,40 @@
microcode = '''
def macroop TEST_M_R
{
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- and "NUM_INTREGS", "NUM_INTREGS+1", "env.reg"
+ ld t1, ds, [scale, index, base], disp
+ and t0, t1, reg
};
def macroop TEST_P_R
{
- rdip "NUM_INTREGS+7"
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- and "NUM_INTREGS", "NUM_INTREGS+1", "env.reg"
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ and t0, t1, reg
};
def macroop TEST_R_R
{
- and "NUM_INTREGS", "env.reg", "env.regm"
+ and t0, reg, regm
};
def macroop TEST_M_I
{
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- limm "NUM_INTREGS+2", "IMMEDIATE"
- and "NUM_INTREGS", "NUM_INTREGS+1", "NUM_INTREGS+2"
+ ld t1, ds, [scale, index, base], disp
+ limm t2, imm
+ and t0, t1, t2
};
def macroop TEST_P_I
{
- rdip "NUM_INTREGS+7"
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- limm "NUM_INTREGS+2", "IMMEDIATE"
- and "NUM_INTREGS", "NUM_INTREGS+1", "NUM_INTREGS+2"
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ limm t2, imm
+ and t0, t1, t2
};
def macroop TEST_R_I
{
- limm "NUM_INTREGS+1", "IMMEDIATE"
- and "NUM_INTREGS", "env.reg", "NUM_INTREGS+1"
+ limm t1, imm
+ and t0, reg, t1
};
'''
diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py
index 5cd8a6359..1372f7dba 100644
--- a/src/arch/x86/isa/insts/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/control_transfer/call.py
@@ -56,13 +56,14 @@
microcode = '''
def macroop CALL_I
{
- .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+ # Make the default data size of pops 64 bits in 64 bit mode
+ .adjust_env oszIn64Override
- limm "NUM_INTREGS+2", "IMMEDIATE"
- rdip "NUM_INTREGS+1"
- subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
- st "NUM_INTREGS+1", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
- wrip "NUM_INTREGS+1", "NUM_INTREGS+2"
+ limm t2, imm
+ rdip t1
+ subi "INTREG_RSP", "INTREG_RSP", dsz
+ st t1, ss, [0, t0, "INTREG_RSP"]
+ wrip t1, t2
};
'''
#let {{
diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py
index 662b2c373..c85dd7cc4 100644
--- a/src/arch/x86/isa/insts/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/data_transfer/move.py
@@ -55,59 +55,55 @@
microcode = '''
def macroop MOV_R_R {
- mov "env.reg", "env.reg", "env.regm"
+ mov reg, reg, regm
};
def macroop MOV_M_R {
- st "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
+ st reg, ds, [scale, index, base], disp
};
def macroop MOV_P_R {
- rdip "NUM_INTREGS+7"
- st "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
+ rdip t7
+ st reg, ds, [scale, index, base], disp
};
def macroop MOV_R_M {
- ld "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
+ ld reg, ds, [scale, index, base], disp
};
def macroop MOV_R_P {
- rdip "NUM_INTREGS+7"
- ld "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
+ rdip t7
+ ld reg, ds, [scale, index, base], disp
};
def macroop MOV_R_I {
- limm "env.reg", "IMMEDIATE"
+ limm reg, imm
};
def macroop MOV_M_I {
- limm "NUM_INTREGS+1", "IMMEDIATE"
- st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ limm t1, imm
+ st t1, ds, [scale, index, base], disp
};
def macroop MOV_P_I {
- rdip "NUM_INTREGS+7"
- limm "NUM_INTREGS+1", "IMMEDIATE"
- st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ rdip t7
+ limm t1, imm
+ st t1, ds, [scale, index, base], disp
};
def macroop MOVSXD_R_R {
- sext "env.reg", "env.regm", "env.dataSize"
+ sext reg, regm, dsz
};
def macroop MOVSXD_R_M {
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- sext "env.reg", "NUM_INTREGS+1", "env.dataSize"
+ ld t1, ds, [scale, index, base], disp
+ sext reg, t1, dsz
};
def macroop MOVSXD_R_P {
- rdip "NUM_INTREGS+7"
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- sext "env.reg", "NUM_INTREGS+1", "env.dataSize"
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ sext reg, t1, dsz
};
'''
#let {{
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index ad95fd468..ca2443752 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -55,21 +55,19 @@
microcode = '''
def macroop POP_R {
-
# Make the default data size of pops 64 bits in 64 bit mode
- .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+ .adjust_env oszIn64Override
- ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
- addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
+ ld reg, ss, [0, t0, "INTREG_RSP"]
+ addi "INTREG_RSP", "INTREG_RSP", dsz
};
def macroop PUSH_R {
-
# Make the default data size of pops 64 bits in 64 bit mode
- .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+ .adjust_env oszIn64Override
- subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
- st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
+ subi "INTREG_RSP", "INTREG_RSP", dsz
+ st reg, ss, [0, t0, "INTREG_RSP"]
};
'''
#let {{
diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py
index f5f92ddbf..dcaf9778e 100644
--- a/src/arch/x86/isa/insts/load_effective_address.py
+++ b/src/arch/x86/isa/insts/load_effective_address.py
@@ -55,11 +55,11 @@
microcode = '''
def macroop LEA_R_M {
- lea "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
+ lea reg, ds, [scale, index, base], disp
};
def macroop LEA_R_P {
- rdip "NUM_INTREGS+7"
- lea "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
+ rdip t7
+ lea reg, ds, [scale, index, base], disp
};
'''
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index d02bfd586..2fd369d60 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -56,74 +56,64 @@
microcode = '''
def macroop XOR_R_R
{
- xor "env.reg", "env.reg", "env.regm"
+ xor reg, reg, regm
};
def macroop XOR_R_I
{
- limm "NUM_INTREGS+1", "IMMEDIATE"
- xor "env.reg", "env.reg", "NUM_INTREGS+1"
+ limm t1, imm
+ xor reg, reg, t1
};
def macroop XOR_M_R
{
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
- st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ ld t1, ds, [scale, index, base], disp
+ xor t1, t1, reg
+ st t1, ds, [scale, index, base], disp
};
def macroop XOR_P_R
{
- rdip "NUM_INTREGS+7"
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
- st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ xor t1, t1, reg
+ st t1, ds, [scale, index, base], disp
};
def macroop XOR_R_M
{
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- xor "env.reg", "env.reg", "NUM_INTREGS+1"
+ ld t1, ds, [scale, index, base], disp
+ xor reg, reg, t1
};
def macroop XOR_R_P
{
- rdip "NUM_INTREGS+7"
- ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- xor "env.reg", "env.reg", "NUM_INTREGS+1"
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ xor reg, reg, t1
};
def macroop AND_R_I
{
- limm "NUM_INTREGS+1", "IMMEDIATE"
- and "env.reg", "env.reg", "NUM_INTREGS+1"
+ limm t1, imm
+ and reg, reg, t1
};
def macroop AND_M_I
{
- ld "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- limm "NUM_INTREGS+1", "IMMEDIATE"
- and "NUM_INTREGS+2", "NUM_INTREGS+2", "NUM_INTREGS+1"
- st "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ ld t2, ds, [scale, index, base], disp
+ limm t1, imm
+ and t2, t2, t1
+ st t2, ds, [scale, index, base], disp
};
def macroop AND_P_I
{
- rdip "NUM_INTREGS+7"
- ld "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
- limm "NUM_INTREGS+1", "IMMEDIATE"
- and "NUM_INTREGS+2", "NUM_INTREGS+2", "NUM_INTREGS+1"
- st "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
- "DISPLACEMENT"
+ rdip t7
+ ld t2, ds, [scale, index, base], disp
+ limm t1, imm
+ and t2, t2, t1
+ st t2, ds, [scale, index, base], disp
};
'''
#let {{
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 50addb33f..4e06f4391 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -72,5 +72,33 @@ let {{
from micro_asm import MicroAssembler, Rom_Macroop, Rom
mainRom = Rom('main ROM')
assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
+ # Add in symbols for the microcode registers
+ for num in range(15):
+ assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
+ # Add in symbols for the segment descriptor registers
+ for letter in ("C", "D", "E", "F", "G", "S"):
+ assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
+ # Miscellaneous symbols
+ symbols = {
+ "reg" : "env.reg",
+ "regm" : "env.regm",
+ "imm" : "IMMEDIATE",
+ "disp" : "DISPLACEMENT",
+ "scale" : "env.scale",
+ "index" : "env.index",
+ "base" : "env.base",
+ "dsz" : "env.dataSize",
+ "osz" : "env.operandSize",
+ "ssz" : "env.stackSize"
+ }
+ assembler.symbols.update(symbols)
+
+ # Code literal which forces a default 64 bit operand size in 64 bit mode.
+ assembler.symbols["oszIn64Override"] = '''
+ if (machInst.mode.submode == SixtyFourBitMode &&
+ env.dataSize == 4)
+ env.dataSize = 8;
+ '''
+
macroopDict = assembler.assemble(microcode)
}};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 7c5b6df01..65b75fab8 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -162,6 +162,7 @@ def template MicroRegOpExecute {{
%(op_decl)s;
%(op_rd)s;
%(code)s;
+ %(flag_code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
@@ -181,6 +182,7 @@ def template MicroRegOpImmExecute {{
%(op_decl)s;
%(op_rd)s;
%(code)s;
+ %(flag_code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
@@ -304,11 +306,11 @@ def template MicroRegOpImmConstructor {{
let {{
class RegOp(X86Microop):
- def __init__(self, dest, src1, src2):
+ def __init__(self, dest, src1, src2, setStatus):
self.dest = dest
self.src1 = src1
self.src2 = src2
- self.setStatus = False
+ self.setStatus = setStatus
self.dataSize = "env.dataSize"
self.ext = 0
@@ -326,11 +328,11 @@ let {{
return allocator
class RegOpImm(X86Microop):
- def __init__(self, dest, src1, imm8):
+ def __init__(self, dest, src1, imm8, setStatus):
self.dest = dest
self.src1 = src1
self.imm8 = imm8
- self.setStatus = False
+ self.setStatus = setStatus
self.dataSize = "env.dataSize"
self.ext = 0
@@ -356,20 +358,22 @@ let {{
decoder_output = ""
exec_output = ""
- def setUpMicroRegOp(name, Name, base, code, child):
+ def setUpMicroRegOp(name, Name, base, code, child, flagCode):
global header_output
global decoder_output
global exec_output
global microopClasses
- iop = InstObjParams(name, Name, base, {"code" : code})
+ iop = InstObjParams(name, Name, base,
+ {"code" : code,
+ "flag_code" : flagCode})
header_output += MicroRegOpDeclare.subst(iop)
decoder_output += MicroRegOpConstructor.subst(iop)
exec_output += MicroRegOpExecute.subst(iop)
microopClasses[name] = child
- def defineMicroRegOp(mnemonic, code):
+ def defineMicroRegOp(mnemonic, code, flagCode):
Name = mnemonic
name = mnemonic.lower()
@@ -382,31 +386,31 @@ let {{
# Build the all register version of this micro op
class RegOpChild(RegOp):
- def __init__(self, dest, src1, src2):
- super(RegOpChild, self).__init__(dest, src1, src2)
+ def __init__(self, dest, src1, src2, setStatus=False):
+ super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
+ setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);
# Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
- def __init__(self, dest, src1, src2):
- super(RegOpChildImm, self).__init__(dest, src1, src2)
+ def __init__(self, dest, src1, src2, setStatus=False):
+ super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
self.className = Name + "Imm"
self.mnemonic = name + "i"
- setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
+ setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);
- defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
- defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
- defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
- defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
- defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
- defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
- defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
- defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
- defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
+ defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
+ defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
+ defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
+ defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
+ defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
+ defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
+ defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
+ defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
+ defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
# This has it's own function because Wr ops have implicit destinations
def defineMicroRegOpWr(mnemonic, code):
@@ -423,20 +427,20 @@ let {{
# Build the all register version of this micro op
class RegOpChild(RegOp):
def __init__(self, src1, src2):
- super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2)
+ super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
+ setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");
# Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
def __init__(self, src1, src2):
- super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2)
+ super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
self.className = Name + "Imm"
self.mnemonic = name + "i"
- setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
+ setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
@@ -447,11 +451,11 @@ let {{
class RegOpChild(RegOp):
def __init__(self, dest, src1 = "NUM_INTREGS"):
- super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS")
+ super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild);
+ setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
@@ -461,11 +465,11 @@ let {{
class RegOpChild(RegOpImm):
def __init__(self, dest, src1, src2):
- super(RegOpChild, self).__init__(dest, src1, src2)
+ super(RegOpChild, self).__init__(dest, src1, src2, False)
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild);
+ setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");
defineMicroRegOpImm('Sext', '''
IntReg val = SrcReg1;
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 14:16:33 +0000