summaryrefslogtreecommitdiff
path: root/src/arch/x86/isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/x86/isa')
-rw-r--r--src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 936fa6973..5355775eb 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -196,6 +196,53 @@ def macroop IMUL_R_P_I
ld t2, ds, [0, t0, t7]
mulel reg, t2, t1
};
+
+#
+# One byte version of unsigned division
+#
+
+def macroop DIV_B_R
+{
+ div1 rax, rax, reg
+};
+
+def macroop DIV_B_M
+{
+ ld t1, ds, [scale, index, base], disp
+ div1 rax, rax, t1
+};
+
+def macroop DIV_B_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ div1 rax, rax, t1
+};
+
+#
+# Unsigned division
+#
+
+def macroop DIV_R
+{
+ divr rdx, rax, reg
+ divq rax, rax, reg
+};
+
+def macroop DIV_M
+{
+ ld t1, ds, [scale, index, base], disp
+ divr rdx, rax, t1
+ divq rax, rax, t1
+};
+
+def macroop DIV_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ divr rdx, rax, t1
+ divq rax, rax, t1
+};
'''
#let {{
# class MUL(Inst):