diff options
Diffstat (limited to 'src/arch/x86/pagetable.hh')
-rw-r--r-- | src/arch/x86/pagetable.hh | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh index 8ca179c86..aaf82ed70 100644 --- a/src/arch/x86/pagetable.hh +++ b/src/arch/x86/pagetable.hh @@ -58,9 +58,14 @@ #ifndef __ARCH_X86_PAGETABLE_HH__ #define __ARCH_X86_PAGETABLE_HH__ +#include <iostream> +#include <string> + #include "sim/host.hh" #include "base/misc.hh" +class Checkpoint; + namespace X86ISA { struct VAddr @@ -68,8 +73,37 @@ namespace X86ISA VAddr(Addr a) { panic("not implemented yet."); } }; - class PageTableEntry + struct TlbEntry { + // The base of the physical page. + Addr pageStart; + // Read permission is always available, assuming it isn't blocked by + // other mechanisms. + bool writeable; + // Whether this page is accesible without being in supervisor mode. + bool user; + // Whether to use write through or write back. M5 ignores this and + // lets the caches handle the writeback policy. + //bool pwt; + // Whether the page is cacheable or not. + bool uncacheable; + // Whether or not to kick this page out on a write to CR3. + bool global; + // A bit used to form an index into the PAT table. + bool patBit; + // Whether or not memory on this page can be executed. + bool noExec; + + // The beginning of the virtual page this entry maps. + Addr vaddr; + // The size of the page this entry represents. + Addr size; + + TlbEntry() {} + TlbEntry(Addr paddr) : pageStart(paddr) {} + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); }; } |