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Diffstat (limited to 'src/arch/x86/tlb.cc')
-rw-r--r--src/arch/x86/tlb.cc40
1 files changed, 36 insertions, 4 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 191e91a00..e954c9c73 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -332,7 +332,20 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
DPRINTF(TLB, "Paging enabled.\n");
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
+ if (mode == Read) {
+ rdAccesses++;
+ } else {
+ wrAccesses++;
+ }
if (!entry) {
+ DPRINTF(TLB, "Handling a TLB miss for "
+ "address %#x at pc %#x.\n",
+ vaddr, tc->instAddr());
+ if (mode == Read) {
+ rdMisses++;
+ } else {
+ wrMisses++;
+ }
if (FullSystem) {
Fault fault = walker->start(tc, translation, req, mode);
if (timing || fault != NoFault) {
@@ -343,10 +356,6 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
entry = lookup(vaddr);
assert(entry);
} else {
- DPRINTF(TLB, "Handling a TLB miss for "
- "address %#x at pc %#x.\n",
- vaddr, tc->instAddr());
-
Process *p = tc->getProcessPtr();
TlbEntry newEntry;
bool success = p->pTable->lookup(vaddr, newEntry);
@@ -445,6 +454,29 @@ TLB::getWalker()
}
void
+TLB::regStats()
+{
+ using namespace Stats;
+
+ rdAccesses
+ .name(name() + ".rdAccesses")
+ .desc("TLB accesses on read requests");
+
+ wrAccesses
+ .name(name() + ".wrAccesses")
+ .desc("TLB accesses on write requests");
+
+ rdMisses
+ .name(name() + ".rdMisses")
+ .desc("TLB misses on read requests");
+
+ wrMisses
+ .name(name() + ".wrMisses")
+ .desc("TLB misses on write requests");
+
+}
+
+void
TLB::serialize(CheckpointOut &cp) const
{
// Only store the entries in use.