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-rw-r--r--src/arch/x86/tlb.hh14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index d036b74d6..c3dc83bb2 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -122,13 +122,11 @@ namespace X86ISA
return ++lruSeq;
}
- Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
- void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, Mode mode);
- /** Stub function for compilation support of CheckerCPU. x86 ISA does
- * not support Checker model at the moment
- */
- Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault translateAtomic(
+ RequestPtr req, ThreadContext *tc, Mode mode) override;
+ void translateTiming(
+ RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode) override;
/**
* Do post-translation physical address finalization.
@@ -144,7 +142,7 @@ namespace X86ISA
* @return A fault on failure, NoFault otherwise.
*/
Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
- Mode mode) const;
+ Mode mode) const override;
TlbEntry * insert(Addr vpn, TlbEntry &entry);