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-rw-r--r--src/arch/x86/isa.hh14
-rw-r--r--src/arch/x86/registers.hh10
2 files changed, 24 insertions, 0 deletions
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 099d27c7c..b61face09 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -82,6 +82,8 @@ namespace X86ISA
return RegId(CCRegClass, flattenCCIndex(regId.index()));
case MiscRegClass:
return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+ default:
+ break;
}
return regId;
}
@@ -103,6 +105,18 @@ namespace X86ISA
}
int
+ flattenVecIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenVecElemIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
flattenCCIndex(int reg) const
{
return reg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index d23731977..9db3349f0 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,6 +41,7 @@
#ifndef __ARCH_X86_REGISTERS_HH__
#define __ARCH_X86_REGISTERS_HH__
+#include "arch/generic/vec_reg.hh"
#include "arch/x86/generated/max_inst_regs.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/ccr.hh"
@@ -93,6 +94,15 @@ typedef uint64_t IntReg;
typedef uint64_t CCReg;
typedef uint64_t MiscReg;
+// dummy typedefs since we don't have vector regs
+constexpr unsigned NumVecElemPerVecReg = 2;
+using VecElem = uint32_t;
+using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
+using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
+using VecRegContainer = VecReg::Container;
+// This has to be one to prevent warnings that are treated as errors
+constexpr unsigned NumVecRegs = 1;
+
//These floating point types are correct for mmx, but not
//technically for x87 (80 bits) or at all for xmm (128 bits)
typedef double FloatReg;