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-rw-r--r--src/arch/x86/SConscript1
-rw-r--r--src/arch/x86/isa.cc101
-rw-r--r--src/arch/x86/isa.hh78
-rw-r--r--src/arch/x86/miscregfile.hh6
-rw-r--r--src/arch/x86/process.cc1
-rw-r--r--src/arch/x86/regfile.cc84
-rw-r--r--src/arch/x86/regfile.hh33
-rw-r--r--src/arch/x86/tlb.cc1
-rw-r--r--src/arch/x86/utility.hh1
9 files changed, 207 insertions, 99 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 4c0460e28..96967ea24 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -96,6 +96,7 @@ if env['TARGET_ISA'] == 'x86':
Source('insts/microregop.cc')
Source('insts/static_inst.cc')
Source('intregfile.cc')
+ Source('isa.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
Source('predecoder.cc')
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
new file mode 100644
index 000000000..4d8c8bb67
--- /dev/null
+++ b/src/arch/x86/isa.cc
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/isa.hh"
+#include "arch/x86/floatregs.hh"
+#include "cpu/thread_context.hh"
+
+namespace X86ISA
+{
+
+void
+ISA::clear()
+{
+ miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+ return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+ return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+ miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+ miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+int
+ISA::flattenIntIndex(int reg)
+{
+ //If we need to fold over the index to match byte semantics, do that.
+ //Otherwise, just strip off any extra bits and pass it through.
+ if (reg & (1 << 6))
+ return (reg & (~(1 << 6) - 0x4));
+ else
+ return (reg & ~(1 << 6));
+}
+
+int
+ISA::flattenFloatIndex(int reg)
+{
+ if (reg >= NUM_FLOATREGS) {
+ int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
+ reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
+ }
+ return reg;
+}
+
+void
+ISA::serialize(EventManager *em, std::ostream &os)
+{
+ miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
+{
+ miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
new file mode 100644
index 000000000..34c803f0c
--- /dev/null
+++ b/src/arch/x86/isa.hh
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_ISA_HH__
+#define __ARCH_X86_ISA_HH__
+
+#include "arch/x86/miscregfile.hh"
+#include "arch/x86/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace X86ISA
+{
+ class ISA
+ {
+ protected:
+ MiscRegFile miscRegFile;
+
+ public:
+ int instAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ int dataAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ void clear();
+
+ MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+ void setMiscRegNoEffect(int miscReg, const MiscReg val);
+ void setMiscReg(int miscReg, const MiscReg val,
+ ThreadContext *tc);
+
+ int flattenIntIndex(int reg);
+ int flattenFloatIndex(int reg);
+
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string &section);
+ };
+}
+
+#endif
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index 74dcbcbea..f2329b7b4 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -99,14 +99,10 @@ class Checkpoint;
namespace X86ISA
{
- //These will have to be updated in the future.
- const int NumMiscArchRegs = NUM_MISCREGS;
- const int NumMiscRegs = NUM_MISCREGS;
-
class MiscRegFile
{
protected:
- MiscReg regVal[NumMiscRegs];
+ MiscReg regVal[NUM_MISCREGS];
void updateHandyM5Reg(Efer efer, CR0 cr0,
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index c643a7924..54c7c9121 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -87,6 +87,7 @@
*/
#include "arch/x86/isa_traits.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/process.hh"
#include "arch/x86/segmentregs.hh"
#include "arch/x86/types.hh"
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 83279902e..f6a9c1480 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -86,6 +86,7 @@
*/
#include "arch/x86/floatregs.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/regfile.hh"
#include "base/trace.hh"
#include "sim/serialize.hh"
@@ -130,28 +131,6 @@ void RegFile::clear()
{
floatRegFile.clear();
intRegFile.clear();
- miscRegFile.clear();
-}
-
-MiscReg RegFile::readMiscRegNoEffect(int miscReg)
-{
- return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
-}
-
-MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
-{
- return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
-}
-
-void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
-{
- miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
-}
-
-void RegFile::setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc)
-{
- miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
}
FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -209,50 +188,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
intRegFile.setReg(intReg, val);
}
-int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
-{
- //If we need to fold over the index to match byte semantics, do that.
- //Otherwise, just strip off any extra bits and pass it through.
- if (reg & (1 << 6))
- return (reg & (~(1 << 6) - 0x4));
- else
- return (reg & ~(1 << 6));
-}
-
-int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
-{
- if (reg >= NUM_FLOATREGS) {
- int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP);
- reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
- }
- return reg;
-}
-
-void
-RegFile::serialize(EventManager *em, std::ostream &os)
-{
- intRegFile.serialize(os);
- floatRegFile.serialize(os);
- miscRegFile.serialize(os);
- SERIALIZE_SCALAR(rip);
- SERIALIZE_SCALAR(nextRip);
-}
-
void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
-{
- intRegFile.unserialize(cp, section);
- floatRegFile.unserialize(cp, section);
- miscRegFile.unserialize(cp, section);
- UNSERIALIZE_SCALAR(rip);
- UNSERIALIZE_SCALAR(nextRip);
-}
-
-void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
- //panic("copyMiscRegs not implemented for x86!\n");
warn("copyMiscRegs is naively implemented for x86\n");
- for (int i = 0; i < X86ISA::NumMiscRegs; ++i) {
+ for (int i = 0; i < NUM_MISCREGS; ++i) {
if ( ( i != MISCREG_CR1 &&
!(i > MISCREG_CR4 && i < MISCREG_CR8) &&
!(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
@@ -260,10 +200,10 @@ void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
}
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}
-
}
-void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
+void
+X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
{
panic("copyRegs not implemented for x86!\n");
//copy int regs
@@ -273,3 +213,17 @@ void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
dest->setPC(src->readPC());
dest->setNextPC(src->readNextPC());
}
+
+void
+RegFile::serialize(EventManager *em, std::ostream &os)
+{
+ intRegFile.serialize(os);
+ floatRegFile.serialize(os);
+}
+
+void
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
+{
+ intRegFile.unserialize(cp, section);
+ floatRegFile.unserialize(cp, section);
+}
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 4f285254a..0414622a2 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -62,8 +62,8 @@
#include "arch/x86/floatregfile.hh"
#include "arch/x86/intregfile.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/isa_traits.hh"
-#include "arch/x86/miscregfile.hh"
#include "arch/x86/types.hh"
#include "base/types.hh"
@@ -72,6 +72,9 @@ class EventManager;
namespace X86ISA
{
+ const int NumMiscArchRegs = NUM_MISCREGS;
+ const int NumMiscRegs = NUM_MISCREGS;
+
class RegFile
{
protected:
@@ -91,33 +94,11 @@ namespace X86ISA
protected:
IntRegFile intRegFile; // integer register file
FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
public:
void clear();
- MiscReg readMiscRegNoEffect(int miscReg);
-
- MiscReg readMiscReg(int miscReg, ThreadContext *tc);
-
- void setMiscRegNoEffect(int miscReg, const MiscReg &val);
-
- void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc);
-
- int instAsid()
- {
- //XXX This doesn't make sense in x86
- return 0;
- }
-
- int dataAsid()
- {
- //XXX This doesn't make sense in x86
- return 0;
- }
-
FloatReg readFloatReg(int floatReg, int width);
FloatReg readFloatReg(int floatReg);
@@ -141,14 +122,8 @@ namespace X86ISA
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
-
- public:
};
- int flattenIntIndex(ThreadContext * tc, int reg);
-
- int flattenFloatIndex(ThreadContext * tc, int reg);
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 1478c3e66..c67c193ea 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -60,6 +60,7 @@
#include "config/full_system.hh"
#include "arch/x86/insts/microldstop.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/pagetable.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 9290dc024..dbb2bc361 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -58,6 +58,7 @@
#ifndef __ARCH_X86_UTILITY_HH__
#define __ARCH_X86_UTILITY_HH__
+#include "arch/x86/miscregs.hh"
#include "arch/x86/types.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 00:11:44 +0000