diff options
Diffstat (limited to 'src/arch/x86')
-rw-r--r-- | src/arch/x86/X86LocalApic.py | 1 | ||||
-rw-r--r-- | src/arch/x86/X86NativeTrace.py | 1 | ||||
-rw-r--r-- | src/arch/x86/X86System.py | 2 | ||||
-rw-r--r-- | src/arch/x86/X86TLB.py | 2 | ||||
-rw-r--r-- | src/arch/x86/bios/ACPI.py | 4 | ||||
-rw-r--r-- | src/arch/x86/bios/E820.py | 2 | ||||
-rw-r--r-- | src/arch/x86/bios/IntelMP.py | 12 | ||||
-rw-r--r-- | src/arch/x86/bios/SMBios.py | 3 |
8 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py index 0bc36612d..5c14679c2 100644 --- a/src/arch/x86/X86LocalApic.py +++ b/src/arch/x86/X86LocalApic.py @@ -46,6 +46,7 @@ from Device import BasicPioDevice class X86LocalApic(BasicPioDevice): type = 'X86LocalApic' cxx_class = 'X86ISA::Interrupts' + cxx_header = 'arch/x86/interrupts.hh' int_master = MasterPort("Port for sending interrupt messages") int_slave = SlavePort("Port for receiving interrupt messages") int_latency = Param.Latency('1ns', \ diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py index cbed77f37..281a2df50 100644 --- a/src/arch/x86/X86NativeTrace.py +++ b/src/arch/x86/X86NativeTrace.py @@ -33,3 +33,4 @@ from NativeTrace import NativeTrace class X86NativeTrace(NativeTrace): type = 'X86NativeTrace' cxx_class = 'Trace::X86NativeTrace' + cxx_header = 'arch/x86/nativetrace.hh' diff --git a/src/arch/x86/X86System.py b/src/arch/x86/X86System.py index 8b294fb86..02185b648 100644 --- a/src/arch/x86/X86System.py +++ b/src/arch/x86/X86System.py @@ -44,6 +44,7 @@ from System import System class X86System(System): type = 'X86System' + cxx_header = 'arch/x86/system.hh' smbios_table = Param.X86SMBiosSMBiosTable( X86SMBiosSMBiosTable(), 'table of smbios/dmi information') intel_mp_pointer = Param.X86IntelMPFloatingPointer( @@ -58,6 +59,7 @@ class X86System(System): class LinuxX86System(X86System): type = 'LinuxX86System' + cxx_header = 'arch/x86/linux/system.hh' e820_table = Param.X86E820Table( X86E820Table(), 'E820 map of physical memory') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 334d2a0cf..a08dbb138 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -44,12 +44,14 @@ from MemObject import MemObject class X86PagetableWalker(MemObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' + cxx_header = 'arch/x86/pagetable_walker.hh' port = MasterPort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") class X86TLB(BaseTLB): type = 'X86TLB' cxx_class = 'X86ISA::TLB' + cxx_header = 'arch/x86/tlb.hh' size = Param.Int(64, "TLB size") walker = Param.X86PagetableWalker(\ X86PagetableWalker(), "page table walker") diff --git a/src/arch/x86/bios/ACPI.py b/src/arch/x86/bios/ACPI.py index 671ed902d..77de42f92 100644 --- a/src/arch/x86/bios/ACPI.py +++ b/src/arch/x86/bios/ACPI.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86ACPISysDescTable(SimObject): type = 'X86ACPISysDescTable' cxx_class = 'X86ISA::ACPI::SysDescTable' + cxx_header = 'arch/x86/bios/acpi.hh' abstract = True oem_id = Param.String('', 'string identifying the oem') @@ -55,12 +56,14 @@ class X86ACPISysDescTable(SimObject): class X86ACPIRSDT(X86ACPISysDescTable): type = 'X86ACPIRSDT' cxx_class = 'X86ISA::ACPI::RSDT' + cxx_header = 'arch/x86/bios/acpi.hh' entries = VectorParam.X86ACPISysDescTable([], 'system description tables') class X86ACPIXSDT(X86ACPISysDescTable): type = 'X86ACPIXSDT' cxx_class = 'X86ISA::ACPI::XSDT' + cxx_header = 'arch/x86/bios/acpi.hh' entries = VectorParam.X86ACPISysDescTable([], 'system description tables') @@ -68,6 +71,7 @@ class X86ACPIXSDT(X86ACPISysDescTable): class X86ACPIRSDP(SimObject): type = 'X86ACPIRSDP' cxx_class = 'X86ISA::ACPI::RSDP' + cxx_header = 'arch/x86/bios/acpi.hh' oem_id = Param.String('', 'string identifying the oem') # Because 0 encodes ACPI 1.0, 2 encodes ACPI 3.0, the version implemented diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py index 78b5faee0..9fa18edbd 100644 --- a/src/arch/x86/bios/E820.py +++ b/src/arch/x86/bios/E820.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86E820Entry(SimObject): type = 'X86E820Entry' cxx_class = 'X86ISA::E820Entry' + cxx_header = 'arch/x86/bios/e820.hh' addr = Param.Addr(0, 'address of the beginning of the region') size = Param.MemorySize('0B', 'size of the region') @@ -49,5 +50,6 @@ class X86E820Entry(SimObject): class X86E820Table(SimObject): type = 'X86E820Table' cxx_class = 'X86ISA::E820Table' + cxx_header = 'arch/x86/bios/e820.hh' entries = VectorParam.X86E820Entry('entries for the e820 table') diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py index 713f62960..21f93eaad 100644 --- a/src/arch/x86/bios/IntelMP.py +++ b/src/arch/x86/bios/IntelMP.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86IntelMPFloatingPointer(SimObject): type = 'X86IntelMPFloatingPointer' cxx_class = 'X86ISA::IntelMP::FloatingPointer' + cxx_header = 'arch/x86/bios/intelmp.hh' # The minor revision of the spec to support. The major version is assumed # to be 1 in accordance with the spec. @@ -53,6 +54,7 @@ class X86IntelMPFloatingPointer(SimObject): class X86IntelMPConfigTable(SimObject): type = 'X86IntelMPConfigTable' cxx_class = 'X86ISA::IntelMP::ConfigTable' + cxx_header = 'arch/x86/bios/intelmp.hh' spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported') oem_id = Param.String("", 'system manufacturer') @@ -80,16 +82,19 @@ class X86IntelMPConfigTable(SimObject): class X86IntelMPBaseConfigEntry(SimObject): type = 'X86IntelMPBaseConfigEntry' cxx_class = 'X86ISA::IntelMP::BaseConfigEntry' + cxx_header = 'arch/x86/bios/intelmp.hh' abstract = True class X86IntelMPExtConfigEntry(SimObject): type = 'X86IntelMPExtConfigEntry' cxx_class = 'X86ISA::IntelMP::ExtConfigEntry' + cxx_header = 'arch/x86/bios/intelmp.hh' abstract = True class X86IntelMPProcessor(X86IntelMPBaseConfigEntry): type = 'X86IntelMPProcessor' cxx_class = 'X86ISA::IntelMP::Processor' + cxx_header = 'arch/x86/bios/intelmp.hh' local_apic_id = Param.UInt8(0, 'local APIC id') local_apic_version = Param.UInt8(0, @@ -106,6 +111,7 @@ class X86IntelMPProcessor(X86IntelMPBaseConfigEntry): class X86IntelMPBus(X86IntelMPBaseConfigEntry): type = 'X86IntelMPBus' cxx_class = 'X86ISA::IntelMP::Bus' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'bus id assigned by the bios') bus_type = Param.String("", 'string that identify the bus type') @@ -118,6 +124,7 @@ class X86IntelMPBus(X86IntelMPBaseConfigEntry): class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry): type = 'X86IntelMPIOAPIC' cxx_class = 'X86ISA::IntelMP::IOAPIC' + cxx_header = 'arch/x86/bios/intelmp.hh' id = Param.UInt8(0, 'id of this APIC') version = Param.UInt8(0, 'bits 0-7 of the version register') @@ -148,6 +155,7 @@ class X86IntelMPTriggerMode(Enum): class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry): type = 'X86IntelMPIOIntAssignment' cxx_class = 'X86ISA::IntelMP::IOIntAssignment' + cxx_header = 'arch/x86/bios/intelmp.hh' interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt') @@ -167,6 +175,7 @@ class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry): class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry): type = 'X86IntelMPLocalIntAssignment' cxx_class = 'X86ISA::IntelMP::LocalIntAssignment' + cxx_header = 'arch/x86/bios/intelmp.hh' interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt') @@ -192,6 +201,7 @@ class X86IntelMPAddressType(Enum): class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry): type = 'X86IntelMPAddrSpaceMapping' cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to') address_type = Param.X86IntelMPAddressType('IOAddress', @@ -202,6 +212,7 @@ class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry): class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry): type = 'X86IntelMPBusHierarchy' cxx_class = 'X86ISA::IntelMP::BusHierarchy' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'id of the bus being described') subtractive_decode = Param.Bool(False, @@ -216,6 +227,7 @@ class X86IntelMPRangeList(Enum): class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry): type = 'X86IntelMPCompatAddrSpaceMod' cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'id of the bus being described') add = Param.Bool(False, diff --git a/src/arch/x86/bios/SMBios.py b/src/arch/x86/bios/SMBios.py index 8fd3d57d8..918d43c2e 100644 --- a/src/arch/x86/bios/SMBios.py +++ b/src/arch/x86/bios/SMBios.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86SMBiosSMBiosStructure(SimObject): type = 'X86SMBiosSMBiosStructure' cxx_class = 'X86ISA::SMBios::SMBiosStructure' + cxx_header = 'arch/x86/bios/smbios.hh' abstract = True class Characteristic(Enum): @@ -93,6 +94,7 @@ class ExtCharacteristic(Enum): class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure): type = 'X86SMBiosBiosInformation' cxx_class = 'X86ISA::SMBios::BiosInformation' + cxx_header = 'arch/x86/bios/smbios.hh' vendor = Param.String("", "vendor name string") version = Param.String("", "version string") @@ -115,6 +117,7 @@ class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure): class X86SMBiosSMBiosTable(SimObject): type = 'X86SMBiosSMBiosTable' cxx_class = 'X86ISA::SMBios::SMBiosTable' + cxx_header = 'arch/x86/bios/smbios.hh' major_version = Param.UInt8(2, "major version number") minor_version = Param.UInt8(5, "minor version number") |