diff options
Diffstat (limited to 'src/arch/x86')
-rw-r--r-- | src/arch/x86/X86TLB.py | 4 | ||||
-rw-r--r-- | src/arch/x86/pagetable_walker.cc | 2 | ||||
-rw-r--r-- | src/arch/x86/pagetable_walker.hh | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 1b2f63d1d..2e61d027f 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -39,9 +39,9 @@ from m5.params import * from m5.proxy import * from m5.objects.BaseTLB import BaseTLB -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class X86PagetableWalker(MemObject): +class X86PagetableWalker(ClockedObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' cxx_header = 'arch/x86/pagetable_walker.hh' diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 0741dc2ed..932eb8eef 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -173,7 +173,7 @@ Walker::getPort(const std::string &if_name, PortID idx) if (if_name == "port") return port; else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index c1f4ed2c4..88b8147cf 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -45,9 +45,9 @@ #include "arch/x86/pagetable.hh" #include "arch/x86/tlb.hh" #include "base/types.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "params/X86PagetableWalker.hh" +#include "sim/clocked_object.hh" #include "sim/faults.hh" #include "sim/system.hh" @@ -55,7 +55,7 @@ class ThreadContext; namespace X86ISA { - class Walker : public MemObject + class Walker : public ClockedObject { protected: // Port for accessing memory @@ -201,7 +201,7 @@ namespace X86ISA } Walker(const Params *params) : - MemObject(params), port(name() + ".port", this), + ClockedObject(params), port(name() + ".port", this), funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system), masterId(sys->getMasterId(this)), numSquashable(params->num_squash_per_cycle), |