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-rw-r--r--src/arch/x86/cpuid.cc2
-rw-r--r--src/arch/x86/faults.cc2
-rw-r--r--src/arch/x86/insts/micromediaop.hh2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/system_calls.py4
-rw-r--r--src/arch/x86/isa/insts/romutil.py8
-rw-r--r--src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py2
-rw-r--r--src/arch/x86/isa/microops/base.isa2
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa10
-rw-r--r--src/arch/x86/isa/microops/regop.isa6
-rw-r--r--src/arch/x86/process.cc2
-rw-r--r--src/arch/x86/process.hh2
11 files changed, 21 insertions, 21 deletions
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index e15dcd331..6817ca742 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -49,7 +49,7 @@ namespace X86ISA {
L2L3CacheAndL2TLB,
APMInfo,
LongModeAddressSize,
-
+
/*
* The following are defined by the spec but not yet implemented
*/
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index b7d9335d4..7724c0217 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -103,7 +103,7 @@ namespace X86ISA
return ss.str();
}
-
+
void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
X86FaultBase::invoke(tc);
diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index cedd16820..1259b6982 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -68,7 +68,7 @@ namespace X86ISA
{
return ext & MediaScalarOp;
}
-
+
int
numItems(int size) const
{
diff --git a/src/arch/x86/isa/insts/general_purpose/system_calls.py b/src/arch/x86/isa/insts/general_purpose/system_calls.py
index d6f1a39bf..59519c0ae 100644
--- a/src/arch/x86/isa/insts/general_purpose/system_calls.py
+++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py
@@ -43,7 +43,7 @@ def macroop SYSCALL_64
# Save the next RIP.
rdip rcx
-
+
# Stick rflags with RF masked into r11.
rflags t2
limm t3, "~RFBit", dataSize=8
@@ -96,7 +96,7 @@ def macroop SYSCALL_COMPAT
# Save the next RIP.
rdip rcx
-
+
# Stick rflags with RF masked into r11.
rflags t2
limm t3, "~RFBit", dataSize=8
diff --git a/src/arch/x86/isa/insts/romutil.py b/src/arch/x86/isa/insts/romutil.py
index 10653e1cc..ed43171bb 100644
--- a/src/arch/x86/isa/insts/romutil.py
+++ b/src/arch/x86/isa/insts/romutil.py
@@ -66,7 +66,7 @@ def rom
wrdh t9, t4, t2, dataSize=8
- #
+ #
# Figure out where the stack should be
#
@@ -74,7 +74,7 @@ def rom
rdsel t11, ss
# Check if we're changing privelege level. At this point we can assume
- # we're going to a DPL that's less than or equal to the CPL.
+ # we're going to a DPL that's less than or equal to the CPL.
rdattr t10, hs, dataSize=8
andi t10, t10, 3, dataSize=8
rdattr t5, cs, dataSize=8
@@ -139,7 +139,7 @@ def rom
# Build up the interrupt stack frame
#
-
+
# Write out the contents of memory
%(errorCodeCode)s
st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8
@@ -173,7 +173,7 @@ def rom
# Put the results into rflags
wrflags t6, t10
-
+
eret
};
'''
diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
index 027747b52..c3df35708 100644
--- a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
@@ -50,7 +50,7 @@ def macroop MOVD_MMX_P {
};
def macroop MOVD_R_MMX {
- mov2int reg, mmxm, size=dsz
+ mov2int reg, mmxm, size=dsz
};
def macroop MOVD_M_MMX {
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index 5798ac4b0..dc36d0edb 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -51,7 +51,7 @@ let {{
let {{
class X86Microop(object):
-
+
generatorNameTemplate = "generate_%s_%d"
generatorTemplate = '''
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index e5f04109f..cdb3b4899 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -214,7 +214,7 @@ let {{
if ext is None:
self.ext = 0
else:
- self.ext = ext
+ self.ext = ext
def getAllocator(self, microFlags):
className = self.className
@@ -926,7 +926,7 @@ let {{
uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = arg1Bits + arg2Bits;
-
+
if (ext & 0x2) {
if (signedOp()) {
int arg1Sign = bits(arg1Bits, sizeBits - 1);
@@ -963,7 +963,7 @@ let {{
uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = arg1Bits - arg2Bits;
-
+
if (ext & 0x2) {
if (signedOp()) {
int arg1Sign = bits(arg1Bits, sizeBits - 1);
@@ -1025,7 +1025,7 @@ let {{
if (ext & 0x4)
resBits += (ULL(1) << (destBits - 1));
-
+
if (multHi())
resBits >>= destBits;
@@ -1050,7 +1050,7 @@ let {{
uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2;
-
+
result = insertBits(result, hiIndex, loIndex, resBits);
}
FpDestReg_uqw = result;
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 15515ed12..ef0c4cb18 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -238,7 +238,7 @@ let {{
global exec_output
# Stick all the code together so it can be searched at once
- allCode = "|".join((code, flag_code, cond_check, else_code,
+ allCode = "|".join((code, flag_code, cond_check, else_code,
cond_control_flag_init))
allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
cond_control_flag_init))
@@ -786,7 +786,7 @@ let {{
PredecfBit = PredecfBit & ~(ext & ECFBit);
//If some combination of the CF bits need to be set, set them.
- if ((ext & (CFBit | ECFBit)) &&
+ if ((ext & (CFBit | ECFBit)) &&
shiftAmt <= dataSize * 8 &&
bits(SrcReg1, shiftAmt - 1)) {
PredcfofBits = PredcfofBits | (ext & CFBit);
@@ -1018,7 +1018,7 @@ let {{
int msb = bits(DestReg, dataSize * 8 - 1);
int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
//If some combination of the CF bits need to be set, set them.
- if ((ext & (CFBit | ECFBit)) &&
+ if ((ext & (CFBit | ECFBit)) &&
(realShiftAmt == 0) ? origCFBit : CFBits) {
PredcfofBits = PredcfofBits | (ext & CFBit);
PredecfBit = PredecfBit | (ext & ECFBit);
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 5a00ce78c..0e3cff937 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -612,7 +612,7 @@ I386LiveProcess::initState()
argsInit(sizeof(uint32_t), PageBytes);
- /*
+ /*
* Set up a GDT for this process. The whole GDT wouldn't really be for
* this process, but the only parts we care about are.
*/
diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 2fb051953..ab513d839 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -74,7 +74,7 @@ namespace X86ISA
public:
Addr gdtStart()
{ return _gdtStart; }
-
+
Addr gdtSize()
{ return _gdtSize; }
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 16:33:20 +0000