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-rw-r--r--src/arch/x86/interrupts.hh6
-rw-r--r--src/arch/x86/pagetable_walker.cc4
-rw-r--r--src/arch/x86/pagetable_walker.hh3
-rw-r--r--src/arch/x86/tlb.cc2
-rw-r--r--src/arch/x86/tlb.hh2
5 files changed, 10 insertions, 7 deletions
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 06425fbda..06094f0b1 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -238,7 +238,8 @@ class Interrupts : public BasicPioDevice, IntDev
AddrRangeList getAddrRanges() const;
AddrRangeList getIntAddrRange() const;
- MasterPort &getMasterPort(const std::string &if_name, int idx = -1)
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID)
{
if (if_name == "int_master") {
return intMasterPort;
@@ -246,7 +247,8 @@ class Interrupts : public BasicPioDevice, IntDev
return BasicPioDevice::getMasterPort(if_name, idx);
}
- SlavePort &getSlavePort(const std::string &if_name, int idx = -1)
+ BaseSlavePort &getSlavePort(const std::string &if_name,
+ PortID idx = InvalidPortID)
{
if (if_name == "int_slave") {
return intSlavePort;
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 46d608ace..1e42e5593 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -173,8 +173,8 @@ bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
return port.sendTimingReq(pkt);
}
-MasterPort &
-Walker::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort &
+Walker::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name == "port")
return port;
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index c59661619..07f476b00 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -169,7 +169,8 @@ namespace X86ISA
RequestPtr req, BaseTLB::Mode mode);
Fault startFunctional(ThreadContext * _tc, Addr &addr,
unsigned &logBytes, BaseTLB::Mode mode);
- MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
protected:
// The TLB we're supposed to load.
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index df7a33ad2..fb7dac02e 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -435,7 +435,7 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
{
}
-MasterPort *
+BaseMasterPort *
TLB::getMasterPort()
{
return &walker->getMasterPort("port");
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 1d1204cfe..85bcead57 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -147,7 +147,7 @@ namespace X86ISA
*
* @return A pointer to the walker master port
*/
- virtual MasterPort *getMasterPort();
+ virtual BaseMasterPort *getMasterPort();
};
}