1 files changed, 50 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index fe7a84511..15bae742a 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -429,4 +429,54 @@ let {{
         code = '''
             FpDestReg.uqw = ~FpSrcReg1.uqw & FpSrcReg2.uqw;
         '''
+
+    class Mminf(MediaOp):
+        code = '''
+            union floatInt
+            {
+                float f;
+                uint32_t i;
+            };
+            union doubleInt
+            {
+                double d;
+                uint64_t i;
+            };
+
+            assert(srcSize == destSize);
+            int size = srcSize;
+            int sizeBits = size * 8;
+            assert(srcSize == 4 || srcSize == 8);
+            int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size);
+            uint64_t result = FpDestReg.uqw;
+
+            for (int i = 0; i < items; i++) {
+                double arg1, arg2;
+                int hiIndex = (i + 1) * sizeBits - 1;
+                int loIndex = (i + 0) * sizeBits;
+                uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex);
+                uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex);
+
+                if (size == 4) {
+                    floatInt fi;
+                    fi.i = arg1Bits;
+                    arg1 = fi.f;
+                    fi.i = arg2Bits;
+                    arg2 = fi.f;
+                } else {
+                    doubleInt di;
+                    di.i = arg1Bits;
+                    arg1 = di.d;
+                    di.i = arg2Bits;
+                    arg2 = di.d;
+                }
+
+                if (arg1 < arg2) {
+                    result = insertBits(result, hiIndex, loIndex, arg1Bits);
+                } else {
+                    result = insertBits(result, hiIndex, loIndex, arg2Bits);
+                }
+            }
+            FpDestReg.uqw = result;
+        '''
 }};