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-rw-r--r--src/arch/x86/tlb.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 17374fa0c..4980c5fe5 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -654,7 +654,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
*/
// Force the access to be uncacheable.
req->setFlags(req->getFlags() | UNCACHEABLE);
- req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr));
+ req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
}
#endif
return NoFault;