summaryrefslogtreecommitdiff
path: root/src/arch/x86
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/tlb.cc4
-rw-r--r--src/arch/x86/tlb.hh5
2 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index acac3081a..208dec177 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -76,7 +76,7 @@
namespace X86ISA {
-TLB::TLB(const Params *p) : SimObject(p), configAddress(0), size(p->size)
+TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
{
tlb = new TlbEntry[size];
std::memset(tlb, 0, sizeof(TlbEntry) * size);
@@ -169,7 +169,7 @@ TLB::invalidateNonGlobal()
}
void
-TLB::demapPage(Addr va)
+TLB::demapPage(Addr va, uint64_t asn)
{
}
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index d08d6fa68..f6ccd5731 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -70,6 +70,7 @@
#include "params/X86DTB.hh"
#include "params/X86ITB.hh"
#include "sim/faults.hh"
+#include "sim/tlb.hh"
#include "sim/sim_object.hh"
class ThreadContext;
@@ -83,7 +84,7 @@ namespace X86ISA
class TLB;
- class TLB : public SimObject
+ class TLB : public BaseTLB
{
protected:
friend class FakeITLBFault;
@@ -120,7 +121,7 @@ namespace X86ISA
void invalidateNonGlobal();
- void demapPage(Addr va);
+ void demapPage(Addr va, uint64_t asn);
protected:
int size;