diff options
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/tlb.cc | 14 | ||||
| -rw-r--r-- | src/arch/x86/tlb.hh | 1 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index a3aec1676..248f929f9 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -338,6 +338,17 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, wrAccesses++; } if (!entry) { + if(req->isSpec()){ + // [InvisiSpec] do not perform TLB fill for + // speculative load + specMisses++; + DPRINTF(TLB, "Get a TLB miss for a speculative load " + "address %#x at pc %#x.\n", + vaddr, tc->instAddr()); + //FIXME: currently reuse the GeneralProtection fault + //instead of creating new faults + return std::make_shared<GeneralProtection>(0); + } DPRINTF(TLB, "Handling a TLB miss for " "address %#x at pc %#x.\n", vaddr, tc->instAddr()); @@ -470,6 +481,9 @@ TLB::regStats() .name(name() + ".wrMisses") .desc("TLB misses on write requests"); + specMisses + .name(name() + ".spec_tlb_misses") + .desc("TLB misses on speculative memory requests"); } void diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 08804a455..9e9c8fa05 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -105,6 +105,7 @@ namespace X86ISA Stats::Scalar wrAccesses; Stats::Scalar rdMisses; Stats::Scalar wrMisses; + Stats::Scalar specMisses; Fault translateInt(RequestPtr req, ThreadContext *tc); |