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-rw-r--r--src/arch/x86/interrupts.cc18
-rw-r--r--src/arch/x86/interrupts.hh6
-rw-r--r--src/arch/x86/utility.cc4
3 files changed, 7 insertions, 21 deletions
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 8eae2d390..c693e6bbd 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -410,9 +410,8 @@ X86ISA::Interrupts::readReg(ApicRegIndex reg)
case APIC_CURRENT_COUNT:
{
if (apicTimerEvent.scheduled()) {
- assert(clock);
// Compute how many m5 ticks happen per count.
- uint64_t ticksPerCount = clock *
+ uint64_t ticksPerCount = clockPeriod() *
divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
// Compute how many m5 ticks are left.
uint64_t val = apicTimerEvent.when() - curTick();
@@ -587,19 +586,20 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
break;
case APIC_INITIAL_COUNT:
{
- assert(clock);
newVal = bits(val, 31, 0);
// Compute how many timer ticks we're being programmed for.
uint64_t newCount = newVal *
(divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
// Schedule on the edge of the next tick plus the new count.
- Tick offset = curTick() % clock;
+ Tick offset = curTick() % clockPeriod();
if (offset) {
reschedule(apicTimerEvent,
- curTick() + (newCount + 1) * clock - offset, true);
+ curTick() + (newCount + 1) *
+ clockPeriod() - offset, true);
} else {
reschedule(apicTimerEvent,
- curTick() + newCount * clock, true);
+ curTick() + newCount *
+ clockPeriod(), true);
}
}
break;
@@ -629,8 +629,6 @@ X86ISA::Interrupts::Interrupts(Params * p) :
pendingIPIs(0), cpu(NULL),
intSlavePort(name() + ".int_slave", this, this, latency)
{
- // Override the default clock
- clock = 0;
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
//Set the local apic DFR to the flat model.
@@ -735,7 +733,6 @@ void
X86ISA::Interrupts::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
- SERIALIZE_SCALAR(clock);
SERIALIZE_SCALAR(pendingSmi);
SERIALIZE_SCALAR(smiVector);
SERIALIZE_SCALAR(pendingNmi);
@@ -761,7 +758,6 @@ void
X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
- UNSERIALIZE_SCALAR(clock);
UNSERIALIZE_SCALAR(pendingSmi);
UNSERIALIZE_SCALAR(smiVector);
UNSERIALIZE_SCALAR(pendingNmi);
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 06094f0b1..4e6ef4324 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -201,12 +201,6 @@ class Interrupts : public BasicPioDevice, IntDev
void setCPU(BaseCPU * newCPU);
- void
- setClock(Tick newClock)
- {
- clock = newClock;
- }
-
const Params *
params() const
{
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index e56e96b99..ae6c37be6 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -174,10 +174,6 @@ void initCPU(ThreadContext *tc, int cpuId)
interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
- // @todo: Control the relative frequency, in this case 16:1, of
- // the clocks in the Python code
- interrupts->setClock(tc->getCpuPtr()->clockPeriod() * 16);
-
// TODO Set the SMRAM base address (SMBASE) to 0x00030000
tc->setMiscReg(MISCREG_VM_CR, 0);