summaryrefslogtreecommitdiff
path: root/src/arch/x86
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/X86TLB.py14
-rw-r--r--src/arch/x86/pagetable_walker.cc2
-rw-r--r--src/arch/x86/tlb.cc61
-rw-r--r--src/arch/x86/tlb.hh48
4 files changed, 22 insertions, 103 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index d5ae95372..15b03fd33 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -68,18 +68,8 @@ if build_env['FULL_SYSTEM']:
class X86TLB(BaseTLB):
type = 'X86TLB'
- abstract = True
- size = Param.Int("TLB size")
+ cxx_class = 'X86ISA::TLB'
+ size = Param.Int(64, "TLB size")
if build_env['FULL_SYSTEM']:
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")
-
-class X86DTB(X86TLB):
- type = 'X86DTB'
- cxx_class = 'X86ISA::DTB'
- size = 64
-
-class X86ITB(X86TLB):
- type = 'X86ITB'
- cxx_class = 'X86ISA::ITB'
- size = 64
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index f625cf4bd..2471c0663 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -98,7 +98,7 @@ Walker::doNext(PacketPtr &write)
bool uncacheable = pte.pcd;
Addr nextRead = 0;
bool doWrite = false;
- bool badNX = pte.nx && (!tlb->allowNX() || !enableNX);
+ bool badNX = pte.nx && execute && enableNX;
switch(state) {
case LongPML4:
DPRINTF(PageTableWalker,
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 3fec4c7da..2feed6f3e 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -700,55 +700,36 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
};
Fault
-DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
+ bool write, bool execute)
{
bool delayedResponse;
return TLB::translate(req, tc, NULL, write,
- false, delayedResponse, false);
+ execute, delayedResponse, false);
}
void
-DTB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write)
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write, bool execute)
{
bool delayedResponse;
assert(translation);
Fault fault = TLB::translate(req, tc, translation,
- write, false, delayedResponse, true);
+ write, execute, delayedResponse, true);
if (!delayedResponse)
- translation->finish(fault, req, tc, write);
-}
-
-Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
-{
- bool delayedResponse;
- return TLB::translate(req, tc, NULL, false,
- true, delayedResponse, false);
-}
-
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation)
-{
- bool delayedResponse;
- assert(translation);
- Fault fault = TLB::translate(req, tc, translation,
- false, true, delayedResponse, true);
- if (!delayedResponse)
- translation->finish(fault, req, tc, false);
+ translation->finish(fault, req, tc, write, execute);
}
#if FULL_SYSTEM
Tick
-DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
return tc->getCpuPtr()->ticks(1);
}
Tick
-DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
return tc->getCpuPtr()->ticks(1);
}
@@ -765,28 +746,10 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
{
}
-void
-DTB::serialize(std::ostream &os)
-{
- TLB::serialize(os);
-}
-
-void
-DTB::unserialize(Checkpoint *cp, const std::string &section)
-{
- TLB::unserialize(cp, section);
-}
-
/* end namespace X86ISA */ }
-X86ISA::ITB *
-X86ITBParams::create()
-{
- return new X86ISA::ITB(this);
-}
-
-X86ISA::DTB *
-X86DTBParams::create()
+X86ISA::TLB *
+X86TLBParams::create()
{
- return new X86ISA::DTB(this);
+ return new X86ISA::TLB(this);
}
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 2467bc472..f67a93d8d 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -67,8 +67,7 @@
#include "config/full_system.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
-#include "params/X86DTB.hh"
-#include "params/X86ITB.hh"
+#include "params/X86TLB.hh"
#include "sim/faults.hh"
#include "sim/tlb.hh"
#include "sim/sim_object.hh"
@@ -82,8 +81,6 @@ namespace X86ISA
static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
- class TLB;
-
class TLB : public BaseTLB
{
protected:
@@ -91,14 +88,9 @@ namespace X86ISA
typedef std::list<TlbEntry *> EntryList;
- bool _allowNX;
uint32_t configAddress;
public:
- bool allowNX() const
- {
- return _allowNX;
- }
typedef X86TLBParams Params;
TLB(const Params *p);
@@ -140,45 +132,19 @@ namespace X86ISA
public:
- TlbEntry * insert(Addr vpn, TlbEntry &entry);
-
- // Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string &section);
- };
-
- class ITB : public TLB
- {
- public:
- typedef X86ITBParams Params;
- ITB(const Params *p) : TLB(p)
- {
- _allowNX = false;
- }
-
- Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc,
+ bool write = false, bool execute = false);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation);
+ Translation *translation,
+ bool write = false, bool execute = false);
- friend class DTB;
- };
-
- class DTB : public TLB
- {
- public:
- typedef X86DTBParams Params;
- DTB(const Params *p) : TLB(p)
- {
- _allowNX = true;
- }
- Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
- void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
#endif
+ TlbEntry * insert(Addr vpn, TlbEntry &entry);
+
// Checkpointing
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 09:06:03 +0000