summaryrefslogtreecommitdiff
path: root/src/arch/x86
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/SConscript41
-rw-r--r--src/arch/x86/X86LocalApic.py2
-rw-r--r--src/arch/x86/X86TLB.py17
-rw-r--r--src/arch/x86/bios/SConscript27
-rw-r--r--src/arch/x86/faults.cc151
-rw-r--r--src/arch/x86/faults.hh10
-rw-r--r--src/arch/x86/interrupts.cc10
-rw-r--r--src/arch/x86/interrupts.hh3
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa4
-rw-r--r--src/arch/x86/isa/includes.isa1
-rw-r--r--src/arch/x86/mmapped_ipr.hh9
-rw-r--r--src/arch/x86/remote_gdb.cc1
-rw-r--r--src/arch/x86/tlb.cc132
-rw-r--r--src/arch/x86/tlb.hh12
-rw-r--r--src/arch/x86/utility.cc17
-rw-r--r--src/arch/x86/utility.hh18
-rw-r--r--src/arch/x86/vtophys.cc7
18 files changed, 190 insertions, 274 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 2742c79e8..3bd968e21 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -53,45 +53,38 @@ if env['TARGET_ISA'] == 'x86':
Source('insts/microop.cc')
Source('insts/microregop.cc')
Source('insts/static_inst.cc')
+ Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/syscalls.cc')
+ Source('linux/system.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
+ Source('pagetable_walker.cc')
Source('predecoder.cc')
Source('predecoder_tables.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
Source('tlb.cc')
Source('types.cc')
Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('X86LocalApic.py')
SimObject('X86NativeTrace.py')
-
+ SimObject('X86System.py')
SimObject('X86TLB.py')
+
+ DebugFlag('Faults', "Trace all faults/exceptions/traps")
+ DebugFlag('LocalApic', "Local APIC debugging")
+ DebugFlag('PageTableWalker', \
+ "Page table walker state machine debugging")
DebugFlag('Predecoder', "Predecoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
- if env['FULL_SYSTEM']:
- DebugFlag('LocalApic', "Local APIC debugging")
- DebugFlag('PageTableWalker', \
- "Page table walker state machine debugging")
- DebugFlag('Faults', "Trace all faults/exceptions/traps")
-
- SimObject('X86LocalApic.py')
- SimObject('X86System.py')
-
- # Full-system sources
- Source('interrupts.cc')
- Source('linux/system.cc')
- Source('pagetable_walker.cc')
- Source('system.cc')
- Source('stacktrace.cc')
- Source('vtophys.cc')
- else:
- Source('process.cc')
-
- Source('linux/linux.cc')
- Source('linux/process.cc')
- Source('linux/syscalls.cc')
-
python_files = (
'__init__.py',
'general_purpose/__init__.py',
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index b9be19b64..2f53c4e24 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -26,7 +26,9 @@
#
# Authors: Gabe Black
+from m5.defines import buildEnv
from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice
class X86LocalApic(BasicPioDevice):
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index ae9bfd353..7f2fcd358 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -35,24 +35,21 @@
#
# Authors: Gabe Black
-from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from BaseTLB import BaseTLB
from MemObject import MemObject
-if buildEnv['FULL_SYSTEM']:
- class X86PagetableWalker(MemObject):
- type = 'X86PagetableWalker'
- cxx_class = 'X86ISA::Walker'
- port = Port("Port for the hardware table walker")
- system = Param.System(Parent.any, "system object")
+class X86PagetableWalker(MemObject):
+ type = 'X86PagetableWalker'
+ cxx_class = 'X86ISA::Walker'
+ port = Port("Port for the hardware table walker")
+ system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
size = Param.Int(64, "TLB size")
- if buildEnv['FULL_SYSTEM']:
- walker = Param.X86PagetableWalker(\
- X86PagetableWalker(), "page table walker")
+ walker = Param.X86PagetableWalker(\
+ X86PagetableWalker(), "page table walker")
diff --git a/src/arch/x86/bios/SConscript b/src/arch/x86/bios/SConscript
index 16a413ed0..abc734ef4 100644
--- a/src/arch/x86/bios/SConscript
+++ b/src/arch/x86/bios/SConscript
@@ -40,20 +40,19 @@
Import('*')
if env['TARGET_ISA'] == 'x86':
- if env['FULL_SYSTEM']:
- # The table generated by the bootloader using the BIOS and passed to
- # the operating system which maps out physical memory.
- SimObject('E820.py')
- Source('e820.cc')
+ # The table generated by the bootloader using the BIOS and passed to
+ # the operating system which maps out physical memory.
+ SimObject('E820.py')
+ Source('e820.cc')
- # The DMI tables.
- SimObject('SMBios.py')
- Source('smbios.cc')
+ # The DMI tables.
+ SimObject('SMBios.py')
+ Source('smbios.cc')
- # Intel Multiprocessor Specification Configuration Table
- SimObject('IntelMP.py')
- Source('intelmp.cc')
+ # Intel Multiprocessor Specification Configuration Table
+ SimObject('IntelMP.py')
+ Source('intelmp.cc')
- # ACPI system description tables
- SimObject('ACPI.py')
- Source('acpi.cc')
+ # ACPI system description tables
+ SimObject('ACPI.py')
+ Source('acpi.cc')
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index feb88fd76..e49bbdbac 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -42,56 +42,53 @@
#include "arch/x86/decoder.hh"
#include "arch/x86/faults.hh"
+#include "arch/x86/isa_traits.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
-#include "arch/x86/isa_traits.hh"
-#include "mem/page_table.hh"
-#include "sim/process.hh"
-#else
-#include "arch/x86/tlb.hh"
#include "debug/Faults.hh"
-#endif
+#include "sim/full_system.hh"
namespace X86ISA
{
-#if FULL_SYSTEM
void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
- PCState pcState = tc->pcState();
- Addr pc = pcState.pc();
- DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
- using namespace X86ISAInst::RomLabels;
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- MicroPC entry;
- if (m5reg.mode == LongMode) {
- if (isSoft()) {
- entry = extern_label_longModeSoftInterrupt;
- } else {
- entry = extern_label_longModeInterrupt;
- }
- } else {
- entry = extern_label_legacyModeInterrupt;
- }
- tc->setIntReg(INTREG_MICRO(1), vector);
- tc->setIntReg(INTREG_MICRO(7), pc);
- if (errorCode != (uint64_t)(-1)) {
+ if (FullSystem) {
+ PCState pcState = tc->pcState();
+ Addr pc = pcState.pc();
+ DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
+ pc, vector, describe());
+ using namespace X86ISAInst::RomLabels;
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ MicroPC entry;
if (m5reg.mode == LongMode) {
- entry = extern_label_longModeInterruptWithError;
+ if (isSoft()) {
+ entry = extern_label_longModeSoftInterrupt;
+ } else {
+ entry = extern_label_longModeInterrupt;
+ }
} else {
- panic("Legacy mode interrupts with error codes "
- "aren't implementde.\n");
+ entry = extern_label_legacyModeInterrupt;
+ }
+ tc->setIntReg(INTREG_MICRO(1), vector);
+ tc->setIntReg(INTREG_MICRO(7), pc);
+ if (errorCode != (uint64_t)(-1)) {
+ if (m5reg.mode == LongMode) {
+ entry = extern_label_longModeInterruptWithError;
+ } else {
+ panic("Legacy mode interrupts with error codes "
+ "aren't implementde.\n");
+ }
+ // Software interrupts shouldn't have error codes. If one
+ // does, there would need to be microcode to set it up.
+ assert(!isSoft());
+ tc->setIntReg(INTREG_MICRO(15), errorCode);
}
- // Software interrupts shouldn't have error codes. If one does,
- // there would need to be microcode to set it up.
- assert(!isSoft());
- tc->setIntReg(INTREG_MICRO(15), errorCode);
+ pcState.upc(romMicroPC(entry));
+ pcState.nupc(romMicroPC(entry) + 1);
+ tc->pcState(pcState);
+ } else {
+ FaultBase::invoke(tc, inst);
}
- pcState.upc(romMicroPC(entry));
- pcState.nupc(romMicroPC(entry) + 1);
- tc->pcState(pcState);
}
std::string
@@ -109,9 +106,12 @@ namespace X86ISA
void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
{
X86FaultBase::invoke(tc);
- // This is the same as a fault, but it happens -after- the instruction.
- PCState pc = tc->pcState();
- pc.uEnd();
+ if (FullSystem) {
+ // This is the same as a fault, but it happens -after- the
+ // instruction.
+ PCState pc = tc->pcState();
+ pc.uEnd();
+ }
}
void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
@@ -119,19 +119,43 @@ namespace X86ISA
panic("Abort exception!");
}
+ void
+ InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
+ {
+ if (FullSystem) {
+ X86Fault::invoke(tc, inst);
+ } else {
+ panic("Unrecognized/invalid instruction executed:\n %s",
+ inst->machInst);
+ }
+ }
+
void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
{
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- X86FaultBase::invoke(tc);
- /*
- * If something bad happens while trying to enter the page fault
- * handler, I'm pretty sure that's a double fault and then all bets are
- * off. That means it should be safe to update this state now.
- */
- if (m5reg.mode == LongMode) {
- tc->setMiscReg(MISCREG_CR2, addr);
+ if (FullSystem) {
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ X86FaultBase::invoke(tc);
+ /*
+ * If something bad happens while trying to enter the page fault
+ * handler, I'm pretty sure that's a double fault and then all
+ * bets are off. That means it should be safe to update this
+ * state now.
+ */
+ if (m5reg.mode == LongMode) {
+ tc->setMiscReg(MISCREG_CR2, addr);
+ } else {
+ tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+ }
} else {
- tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+ PageFaultErrorCode code = errorCode;
+ const char *modeStr = "";
+ if (code.fetch)
+ modeStr = "execute";
+ else if (code.write)
+ modeStr = "write";
+ else
+ modeStr = "read";
+ panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
}
}
@@ -268,30 +292,5 @@ namespace X86ISA
tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
}
-
-#else
-
- void
- InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
- {
- panic("Unrecognized/invalid instruction executed:\n %s",
- inst->machInst);
- }
-
- void
- PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
- {
- PageFaultErrorCode code = errorCode;
- const char *modeStr = "";
- if (code.fetch)
- modeStr = "execute";
- else if (code.write)
- modeStr = "write";
- else
- modeStr = "read";
- panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
- }
-
-#endif
} // namespace X86ISA
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index fba2a26b5..94a2ffcc2 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -85,12 +85,10 @@ namespace X86ISA
return false;
}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
virtual std::string describe() const;
-#endif
};
// Base class for x86 faults which behave as if the underlying instruction
@@ -114,10 +112,8 @@ namespace X86ISA
: X86FaultBase(name, mnem, vector, _errorCode)
{}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
// Base class for x86 aborts which seem to be catastrophic failures.
@@ -129,10 +125,8 @@ namespace X86ISA
: X86FaultBase(name, mnem, vector, _errorCode)
{}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
// Base class for x86 interrupts.
@@ -246,10 +240,8 @@ namespace X86ISA
X86Fault("Invalid-Opcode", "#UD", 6)
{}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class DeviceNotAvailable : public X86Fault
@@ -334,9 +326,7 @@ namespace X86ISA
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#if FULL_SYSTEM
virtual std::string describe() const;
-#endif
};
class X87FpExceptionPending : public X86Fault
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 9944f4afd..612244f49 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -47,6 +47,7 @@
#include "dev/x86/south_bridge.hh"
#include "mem/packet_access.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
int
divideFromConf(uint32_t conf)
@@ -273,8 +274,9 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector,
pendingUnmaskableInt = pendingStartup = true;
startupVector = vector;
}
- }
- cpu->wakeup();
+ }
+ if (FullSystem)
+ cpu->wakeup();
}
@@ -302,10 +304,6 @@ X86ISA::Interrupts::init()
//
BasicPioDevice::init();
IntDev::init();
-
- Pc * pc = dynamic_cast<Pc *>(platform);
- assert(pc);
- pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
}
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 6cf50e2fe..8567b30f0 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -176,6 +176,9 @@ class Interrupts : public BasicPioDevice, IntDev
int initialApicId;
public:
+
+ int getInitialApicId() { return initialApicId; }
+
/*
* Params stuff.
*/
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 4a5cf32d0..4ebf23032 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -394,7 +394,7 @@
default: Inst::RET_FAR();
}
0x4: int3();
- 0x5: decode FULL_SYSTEM default int_Ib() {
+ 0x5: decode FullSystem default int_Ib() {
0: decode IMMEDIATE {
// Really only the LSB matters, but the predecoder
// will sign extend it, and there's no easy way to
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 2471b61ce..030e36404 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -216,7 +216,7 @@
default: Inst::UD2();
}
}
- 0x05: decode FULL_SYSTEM {
+ 0x05: decode FullSystem {
0: SyscallInst::syscall('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: decode MODE_MODE {
@@ -398,7 +398,7 @@
0x1: Inst::RDTSC();
0x2: Inst::RDMSR();
0x3: rdpmc();
- 0x4: decode FULL_SYSTEM {
+ 0x4: decode FullSystem {
0: SyscallInst::sysenter('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: sysenter();
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 237b29877..9a9759c7a 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -84,6 +84,7 @@ output decoder {{
#include "base/misc.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+#include "sim/full_system.hh"
#if defined(linux) || defined(__APPLE__)
#include <fenv.h>
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 525f54bfb..054f280a8 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -47,7 +47,6 @@
*/
#include "arch/x86/regs/misc.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
@@ -57,25 +56,18 @@ namespace X86ISA
inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt)
{
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data = htog(xc->readMiscReg(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->setData(((uint8_t *)&data) + offset);
-#endif
return xc->getCpuPtr()->ticks(1);
}
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data;
@@ -84,7 +76,6 @@ namespace X86ISA
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->writeData(((uint8_t *)&data) + offset);
xc->setMiscReg(index, gtoh(data));
-#endif
return xc->getCpuPtr()->ticks(1);
}
};
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 8db7a6088..c7bce59bf 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -47,7 +47,6 @@
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
using namespace std;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 131909e50..ff65eb04c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -44,23 +44,19 @@
#include "arch/x86/regs/msr.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/pagetable.hh"
+#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
-#include "mem/request.hh"
-
-#if FULL_SYSTEM
-#include "arch/x86/pagetable_walker.hh"
-#else
#include "mem/page_table.hh"
+#include "mem/request.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
-#endif
namespace X86ISA {
@@ -72,10 +68,8 @@ TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
for (int x = 0; x < size; x++)
freeList.push_back(&tlb[x]);
-#if FULL_SYSTEM
walker = p->walker;
walker->setTLB(this);
-#endif
}
TlbEntry *
@@ -293,40 +287,40 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
if (!entry) {
-#if FULL_SYSTEM
- Fault fault = walker->start(tc, translation, req, mode);
- if (timing || fault != NoFault) {
- // This gets ignored in atomic mode.
- delayedResponse = true;
- return fault;
- }
- entry = lookup(vaddr);
- assert(entry);
-#else
- DPRINTF(TLB, "Handling a TLB miss for "
- "address %#x at pc %#x.\n",
- vaddr, tc->instAddr());
-
- Process *p = tc->getProcessPtr();
- TlbEntry newEntry;
- bool success = p->pTable->lookup(vaddr, newEntry);
- if (!success && mode != Execute) {
- // Check if we just need to grow the stack.
- if (p->fixupStackFault(vaddr)) {
- // If we did, lookup the entry for the new page.
- success = p->pTable->lookup(vaddr, newEntry);
+ if (FullSystem) {
+ Fault fault = walker->start(tc, translation, req, mode);
+ if (timing || fault != NoFault) {
+ // This gets ignored in atomic mode.
+ delayedResponse = true;
+ return fault;
}
- }
- if (!success) {
- return new PageFault(vaddr, true, mode, true, false);
+ entry = lookup(vaddr);
+ assert(entry);
} else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
- newEntry.pageStart());
- entry = insert(alignedVaddr, newEntry);
+ DPRINTF(TLB, "Handling a TLB miss for "
+ "address %#x at pc %#x.\n",
+ vaddr, tc->instAddr());
+
+ Process *p = tc->getProcessPtr();
+ TlbEntry newEntry;
+ bool success = p->pTable->lookup(vaddr, newEntry);
+ if (!success && mode != Execute) {
+ // Check if we just need to grow the stack.
+ if (p->fixupStackFault(vaddr)) {
+ // If we did, lookup the entry for the new page.
+ success = p->pTable->lookup(vaddr, newEntry);
+ }
+ }
+ if (!success) {
+ return new PageFault(vaddr, true, mode, true, false);
+ } else {
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
+ newEntry.pageStart());
+ entry = insert(alignedVaddr, newEntry);
+ }
+ DPRINTF(TLB, "Miss was serviced.\n");
}
- DPRINTF(TLB, "Miss was serviced.\n");
-#endif
}
DPRINTF(TLB, "Entry found with paddr %#x, "
@@ -366,27 +360,29 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
req->setPaddr(vaddr);
}
// Check for an access to the local APIC
-#if FULL_SYSTEM
- LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
- Addr baseAddr = localApicBase.base * PageBytes;
- Addr paddr = req->getPaddr();
- if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
- // The Intel developer's manuals say the below restrictions apply,
- // but the linux kernel, because of a compiler optimization, breaks
- // them.
- /*
- // Check alignment
- if (paddr & ((32/8) - 1))
- return new GeneralProtection(0);
- // Check access size
- if (req->getSize() != (32/8))
- return new GeneralProtection(0);
- */
- // Force the access to be uncacheable.
- req->setFlags(Request::UNCACHEABLE);
- req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
+ if (FullSystem) {
+ LocalApicBase localApicBase =
+ tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
+ Addr baseAddr = localApicBase.base * PageBytes;
+ Addr paddr = req->getPaddr();
+ if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
+ // The Intel developer's manuals say the below restrictions apply,
+ // but the linux kernel, because of a compiler optimization, breaks
+ // them.
+ /*
+ // Check alignment
+ if (paddr & ((32/8) - 1))
+ return new GeneralProtection(0);
+ // Check access size
+ if (req->getSize() != (32/8))
+ return new GeneralProtection(0);
+ */
+ // Force the access to be uncacheable.
+ req->setFlags(Request::UNCACHEABLE);
+ req->setPaddr(x86LocalAPICAddress(tc->contextId(),
+ paddr - baseAddr));
+ }
}
-#endif
return NoFault;
};
@@ -409,28 +405,12 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(fault, req, tc, mode);
}
-#if FULL_SYSTEM
-
-Tick
-TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
-{
- return tc->getCpuPtr()->ticks(1);
-}
-
-Tick
-TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
-{
- return tc->getCpuPtr()->ticks(1);
-}
-
Walker *
TLB::getWalker()
{
return walker;
}
-#endif
-
void
TLB::serialize(std::ostream &os)
{
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index e4ea0e1b7..449ca19ce 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -46,7 +46,6 @@
#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
-#include "config/full_system.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
@@ -85,15 +84,11 @@ namespace X86ISA
EntryList::iterator lookupIt(Addr va, bool update_lru = true);
-#if FULL_SYSTEM
- protected:
-
Walker * walker;
+
public:
Walker *getWalker();
-#endif
- public:
void invalidateAll();
void invalidateNonGlobal();
@@ -120,11 +115,6 @@ namespace X86ISA
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
-#if FULL_SYSTEM
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
-
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 29c770f3d..678467672 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -38,11 +38,7 @@
* Authors: Gabe Black
*/
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
#include "arch/x86/interrupts.hh"
-#endif
#include "arch/x86/registers.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/utility.hh"
@@ -55,15 +51,10 @@ namespace X86ISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
panic("getArgument() not implemented for x86!\n");
-#else
- panic("getArgument() only implemented for FULL_SYSTEM\n");
M5_DUMMY_RETURN
-#endif
}
-# if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
@@ -193,12 +184,9 @@ void initCPU(ThreadContext *tc, int cpuId)
tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
}
-#endif
-
void startupCPU(ThreadContext *tc, int cpuId)
{
-#if FULL_SYSTEM
- if (cpuId == 0) {
+ if (cpuId == 0 || !FullSystem) {
tc->activate(0);
} else {
// This is an application processor (AP). It should be initialized to
@@ -206,9 +194,6 @@ void startupCPU(ThreadContext *tc, int cpuId)
// a halted state.
tc->suspend(0);
}
-#else
- tc->activate(0);
-#endif
}
void
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 4cfbe77db..f120ea6c7 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -45,9 +45,9 @@
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
class ThreadContext;
@@ -68,12 +68,12 @@ namespace X86ISA
static inline bool
inUserMode(ThreadContext *tc)
{
-#if FULL_SYSTEM
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- return m5reg.cpl == 3;
-#else
- return true;
-#endif
+ if (!FullSystem) {
+ return true;
+ } else {
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ return m5reg.cpl == 3;
+ }
}
/**
@@ -83,12 +83,8 @@ namespace X86ISA
template <class TC>
void zeroRegisters(TC *tc);
-#if FULL_SYSTEM
-
void initCPU(ThreadContext *tc, int cpuId);
-#endif
-
void startupCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
index 60ce37131..e4abfca59 100644
--- a/src/arch/x86/vtophys.cc
+++ b/src/arch/x86/vtophys.cc
@@ -43,7 +43,6 @@
#include "arch/x86/tlb.hh"
#include "arch/x86/vtophys.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "debug/VtoPhys.hh"
#include "sim/fault_fwd.hh"
@@ -55,16 +54,12 @@ namespace X86ISA
Addr
vtophys(Addr vaddr)
{
-#if FULL_SYSTEM
panic("Need access to page tables\n");
-#endif
- return vaddr;
}
Addr
vtophys(ThreadContext *tc, Addr vaddr)
{
-#if FULL_SYSTEM
Walker *walker = tc->getDTBPtr()->getWalker();
Addr size;
Addr addr = vaddr;
@@ -75,7 +70,5 @@ namespace X86ISA
Addr paddr = addr | masked_addr;
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
-#endif
- return vaddr;
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 16:52:34 +0000