diff options
Diffstat (limited to 'src/arch/x86')
-rw-r--r-- | src/arch/x86/intmessage.hh | 8 | ||||
-rw-r--r-- | src/arch/x86/pagetable_walker.cc | 14 | ||||
-rw-r--r-- | src/arch/x86/pagetable_walker.hh | 14 | ||||
-rw-r--r-- | src/arch/x86/tlb.cc | 12 | ||||
-rw-r--r-- | src/arch/x86/tlb.hh | 10 |
5 files changed, 31 insertions, 27 deletions
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh index 6bf180432..83d80bb94 100644 --- a/src/arch/x86/intmessage.hh +++ b/src/arch/x86/intmessage.hh @@ -79,9 +79,11 @@ namespace X86ISA static inline PacketPtr prepIntRequest(const uint8_t id, Addr offset, Addr size) { - RequestPtr req = new Request(x86InterruptAddress(id, offset), - size, Request::UNCACHEABLE, - Request::intMasterId); + RequestPtr req = std::make_shared<Request>( + x86InterruptAddress(id, offset), + size, Request::UNCACHEABLE, + Request::intMasterId); + PacketPtr pkt = new Packet(req, MemCmd::MessageReq); pkt->allocate(); return pkt; diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 998ea856a..11ec12245 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -68,7 +68,7 @@ namespace X86ISA { Fault Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation, - RequestPtr _req, BaseTLB::Mode _mode) + const RequestPtr &_req, BaseTLB::Mode _mode) { // TODO: in timing mode, instead of blocking when there are other // outstanding requests, see if this request can be coalesced with @@ -514,8 +514,8 @@ Walker::WalkerState::stepWalk(PacketPtr &write) //If we didn't return, we're setting up another read. Request::Flags flags = oldRead->req->getFlags(); flags.set(Request::UNCACHEABLE, uncacheable); - RequestPtr request = - new Request(nextRead, oldRead->getSize(), flags, walker->masterId); + RequestPtr request = std::make_shared<Request>( + nextRead, oldRead->getSize(), flags, walker->masterId); read = new Packet(request, MemCmd::ReadReq); read->allocate(); // If we need to write, adjust the read packet to write the modified @@ -526,7 +526,6 @@ Walker::WalkerState::stepWalk(PacketPtr &write) write->cmd = MemCmd::WriteReq; } else { write = NULL; - delete oldRead->req; delete oldRead; } } @@ -537,7 +536,6 @@ void Walker::WalkerState::endWalk() { nextState = Ready; - delete read->req; delete read; read = NULL; } @@ -584,8 +582,10 @@ Walker::WalkerState::setupWalk(Addr vaddr) Request::Flags flags = Request::PHYSICAL; if (cr3.pcd) flags.set(Request::UNCACHEABLE); - RequestPtr request = new Request(topAddr, dataSize, flags, - walker->masterId); + + RequestPtr request = std::make_shared<Request>( + topAddr, dataSize, flags, walker->masterId); + read = new Packet(request, MemCmd::ReadReq); read->allocate(); } diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index d5aa631d2..edca24795 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -113,12 +113,12 @@ namespace X86ISA bool started; public: WalkerState(Walker * _walker, BaseTLB::Translation *_translation, - RequestPtr _req, bool _isFunctional = false) : - walker(_walker), req(_req), state(Ready), - nextState(Ready), inflight(0), - translation(_translation), - functional(_isFunctional), timing(false), - retrying(false), started(false) + const RequestPtr &_req, bool _isFunctional = false) : + walker(_walker), req(_req), state(Ready), + nextState(Ready), inflight(0), + translation(_translation), + functional(_isFunctional), timing(false), + retrying(false), started(false) { } void initState(ThreadContext * _tc, BaseTLB::Mode _mode, @@ -157,7 +157,7 @@ namespace X86ISA public: // Kick off the state machine. Fault start(ThreadContext * _tc, BaseTLB::Translation *translation, - RequestPtr req, BaseTLB::Mode mode); + const RequestPtr &req, BaseTLB::Mode mode); Fault startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode); BaseMasterPort &getMasterPort(const std::string &if_name, diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index a3aec1676..8e83208f4 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -170,7 +170,7 @@ TLB::demapPage(Addr va, uint64_t asn) } Fault -TLB::translateInt(RequestPtr req, ThreadContext *tc) +TLB::translateInt(const RequestPtr &req, ThreadContext *tc) { DPRINTF(TLB, "Addresses references internal memory.\n"); Addr vaddr = req->getVaddr(); @@ -224,7 +224,8 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) } Fault -TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +TLB::finalizePhysical(const RequestPtr &req, + ThreadContext *tc, Mode mode) const { Addr paddr = req->getPaddr(); @@ -265,7 +266,8 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const } Fault -TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, +TLB::translate(const RequestPtr &req, + ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing) { Request::Flags flags = req->getFlags(); @@ -425,14 +427,14 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, } Fault -TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) +TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) { bool delayedResponse; return TLB::translate(req, tc, NULL, mode, delayedResponse, false); } void -TLB::translateTiming(RequestPtr req, ThreadContext *tc, +TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) { bool delayedResponse; diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 08804a455..827ab8166 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -106,9 +106,9 @@ namespace X86ISA Stats::Scalar rdMisses; Stats::Scalar wrMisses; - Fault translateInt(RequestPtr req, ThreadContext *tc); + Fault translateInt(const RequestPtr &req, ThreadContext *tc); - Fault translate(RequestPtr req, ThreadContext *tc, + Fault translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing); @@ -123,9 +123,9 @@ namespace X86ISA } Fault translateAtomic( - RequestPtr req, ThreadContext *tc, Mode mode) override; + const RequestPtr &req, ThreadContext *tc, Mode mode) override; void translateTiming( - RequestPtr req, ThreadContext *tc, + const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override; /** @@ -141,7 +141,7 @@ namespace X86ISA * @param mode Request type (read/write/execute). * @return A fault on failure, NoFault otherwise. */ - Fault finalizePhysical(RequestPtr req, ThreadContext *tc, + Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const override; TlbEntry *insert(Addr vpn, const TlbEntry &entry); |