diff options
Diffstat (limited to 'src/arch/x86')
25 files changed, 910 insertions, 292 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 2e2c5b006..6de243c9c 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -85,6 +85,7 @@ Import('*') if env['TARGET_ISA'] == 'x86': + Source('emulenv.cc') Source('floatregfile.cc') Source('intregfile.cc') Source('miscregfile.cc') diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc new file mode 100644 index 000000000..e3f703cff --- /dev/null +++ b/src/arch/x86/emulenv.cc @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/emulenv.hh" +#include "base/misc.hh" + +using namespace X86ISA; + +void EmulEnv::doModRM(const ExtMachInst & machInst) +{ + assert(machInst.modRM.mod != 3); + //Use the SIB byte for addressing if the modrm byte calls for it. + if (machInst.modRM.rm == 4 && machInst.addrSize != 2) { + scale = 1 << machInst.sib.scale; + index = machInst.sib.index; + base = machInst.sib.base; + //In this special case, we don't use a base. The displacement also + //changes, but that's managed by the predecoder. + if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0) + base = NUM_INTREGS; + //In -this- special case, we don't use an index. + if (machInst.sib.index == INTREG_RSP) + index = NUM_INTREGS; + } else { + if (machInst.addrSize == 2) { + warn("I'm not really using 16 bit MODRM like I'm supposed to!\n"); + } else { + scale = 0; + base = machInst.modRM.rm; + if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) { + base = NUM_INTREGS; + if (machInst.mode.submode == SixtyFourBitMode) + base = NUM_INTREGS+7; + } + } + } +} + diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh new file mode 100644 index 000000000..66c56fb79 --- /dev/null +++ b/src/arch/x86/emulenv.hh @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_EMULENV_HH__ +#define __ARCH_X86_EMULENV_HH__ + +#include "arch/x86/types.hh" +#include "arch/x86/intregs.hh" + +namespace X86ISA +{ + struct EmulEnv + { + RegIndex reg; + RegIndex regm; + uint8_t scale; + RegIndex index; + RegIndex base; + int dataSize; + int addressSize; + int stackSize; + + EmulEnv(RegIndex _reg, RegIndex _regm, + int _dataSize, int _addressSize, int _stackSize) : + reg(_reg), regm(_regm), + scale(0), index(NUM_INTREGS), + base(NUM_INTREGS), + dataSize(_dataSize), addressSize(_addressSize), + stackSize(_stackSize) + {;} + + void doModRM(const ExtMachInst & machInst); + }; +}; + +#endif // __ARCH_X86_TYPES_HH__ diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh index fc2098716..1b5777f01 100644 --- a/src/arch/x86/intregs.hh +++ b/src/arch/x86/intregs.hh @@ -150,4 +150,4 @@ namespace X86ISA }; }; -#endif // __ARCH_X86_INTERRUPTS_HH__ +#endif // __ARCH_X86_INTREGS_HH__ diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index b72b2b16a..484f8160d 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -63,8 +63,14 @@ 0x00: decode OPCODE_OP_BOTTOM3 { 0x4: ADD(); 0x5: ADD(); - 0x6: push_ES(); - 0x7: pop_ES(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_ES(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pop_ES(); + } default: ADD(); } 0x01: decode OPCODE_OP_BOTTOM3 { @@ -74,7 +80,10 @@ 0x3: or_Gv_Ev(); 0x4: or_Al_Ib(); 0x5: or_rAX_Iz(); - 0x6: push_CS(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_CS(); + } //Any time this is seen, it should generate a two byte opcode 0x7: M5InternalError::error( {{"Saw a one byte opcode whose value was 0x0F!"}}); @@ -86,8 +95,14 @@ 0x3: adc_Gv_Ev(); 0x4: adc_Al_Ib(); 0x5: adc_rAX_Iz(); - 0x6: push_SS(); - 0x7: pop_SS(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_SS(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pop_SS(); + } } 0x03: decode OPCODE_OP_BOTTOM3 { 0x0: sbb_Eb_Gb(); @@ -96,8 +111,14 @@ 0x3: sbb_Gv_Ev(); 0x4: sbb_Al_Ib(); 0x5: sbb_rAX_Iz(); - 0x6: push_DS(); - 0x7: pop_DS(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_DS(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pop_DS(); + } } 0x04: decode OPCODE_OP_BOTTOM3 { 0x0: and_Eb_Gb(); @@ -108,7 +129,10 @@ 0x5: and_rAX_Iz(); 0x6: M5InternalError::error( {{"Tried to execute the ES segment override prefix!"}}); - 0x7: daa(); + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: daa(); + } } 0x05: decode OPCODE_OP_BOTTOM3 { 0x0: sub_Eb_Gb(); @@ -126,7 +150,10 @@ 0x5: Inst::XOR(rAx,Iz); 0x6: M5InternalError::error( {{"Tried to execute the SS segment override prefix!"}}); - 0x7: aaa(); + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aaa(); + } default: MultiInst::XOR(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev]); @@ -140,53 +167,78 @@ 0x5: cmp_rAX_Iz(); 0x6: M5InternalError::error( {{"Tried to execute the DS segment override prefix!"}}); - 0x7: aas(); - } - 0x08: decode OPCODE_OP_BOTTOM3 { - 0x0: inc_eAX(); - 0x1: inc_eCX(); - 0x2: inc_eDX(); - 0x3: inc_eBX(); - 0x4: inc_eSP(); - 0x5: inc_eBP(); - 0x6: inc_eSI(); - 0x7: inc_eDI(); + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aas(); + } } - 0x09: decode OPCODE_OP_BOTTOM3 { - 0x0: dec_eAX(); - 0x1: dec_eCX(); - 0x2: dec_eDX(); - 0x3: dec_eBX(); - 0x4: dec_eSP(); - 0x5: dec_eBP(); - 0x6: dec_eSI(); - 0x7: dec_eDI(); + 0x08: decode MODE_SUBMODE { + 0x0: M5InternalError::error ( + {{"Tried to execute an REX prefix!"}}); + default: decode OPCODE_OP_BOTTOM3 { + 0x0: inc_eAX(); + 0x1: inc_eCX(); + 0x2: inc_eDX(); + 0x3: inc_eBX(); + 0x4: inc_eSP(); + 0x5: inc_eBP(); + 0x6: inc_eSI(); + 0x7: inc_eDI(); + } } - 0x0A: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::PUSH(rAx); - 0x1: push_rCX(); - 0x2: push_rDX(); - 0x3: push_rBX(); - 0x4: Inst::PUSH(rSP); - 0x5: push_rBP(); - 0x6: push_rSI(); - 0x7: push_rDI(); + 0x09: decode MODE_SUBMODE { + 0x0: M5InternalError::error ( + {{"Tried to execute an REX prefix!"}}); + default: decode OPCODE_OP_BOTTOM3 { + 0x0: dec_eAX(); + 0x1: dec_eCX(); + 0x2: dec_eDX(); + 0x3: dec_eBX(); + 0x4: dec_eSP(); + 0x5: dec_eBP(); + 0x6: dec_eSI(); + 0x7: dec_eDI(); + } } - 0x0B: decode OPCODE_OP_BOTTOM3 { - 0x0: pop_rAX(); - 0x1: pop_rCX(); - 0x2: pop_rDX(); - 0x3: pop_rBX(); - 0x4: pop_rSP(); - 0x5: pop_rBP(); - 0x6: Inst::POP(rSI); - 0x7: pop_rDI(); + format Inst { + 0x0A: decode OPCODE_OP_BOTTOM3 { + 0x0: PUSH(rAx); + 0x1: PUSH(rCx); + 0x2: PUSH(rDx); + 0x3: PUSH(rBx); + 0x4: PUSH(rSP); + 0x5: PUSH(rBP); + 0x6: PUSH(rSI); + 0x7: PUSH(rDI); + } + 0x0B: decode OPCODE_OP_BOTTOM3 { + 0x0: POP(rAx); + 0x1: POP(rCx); + 0x2: POP(rDx); + 0x3: POP(rBx); + 0x4: POP(rSP); + 0x5: POP(rBP); + 0x6: POP(rSI); + 0x7: POP(rDI); + } } 0x0C: decode OPCODE_OP_BOTTOM3 { - 0x0: pusha(); - 0x1: popa(); - 0x2: bound_Gv_Ma(); - 0x3: arpl_Ew_Gw(); + 0x0: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pusha(); + } + 0x1: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: popa(); + } + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: bound_Gv_Ma(); + } + 0x3: decode MODE_SUBMODE { + 0x0: Inst::MOVSXD(Gv,Ed); + default: arpl_Ew_Gw(); + } 0x4: M5InternalError::error( {{"Tried to execute the FS segment override prefix!"}}); 0x5: M5InternalError::error( @@ -228,8 +280,21 @@ } 0x10: decode OPCODE_OP_BOTTOM3 { 0x0: group1_Eb_Ib(); - 0x1: group1_Ev_Iz(); - 0x2: group1_Eb_Ib(); + //0x1: group1_Ev_Iz(); + 0x1: decode MODRM_REG { + 0x0: add_Ev_Iz(); + 0x1: or_Ev_Ibz(); + 0x2: adc_Ev_Iz(); + 0x3: sbb_Ev_Iz(); + 0x4: Inst::AND(Ev,Iz); + 0x5: Inst::SUB(Ev,Iz); + 0x6: xor_Ev_Iz(); + 0x7: cmp_Ev_Iz(); + } + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: group1_Eb_Ib(); + } //0x3: group1_Ev_Ib(); 0x3: decode MODRM_REG { 0x0: add_Eb_Ib(); @@ -241,8 +306,8 @@ 0x6: xor_Eb_Ib(); 0x7: cmp_Eb_Ib(); } - 0x4: test_Eb_Gb(); - 0x5: test_Ev_Gv(); + 0x4: Inst::TEST(Eb,Gb); + 0x5: Inst::TEST(Ev,Gv); 0x6: xchg_Eb_Gb(); 0x7: xchg_Ev_Gv(); } @@ -250,14 +315,14 @@ 0x0: Inst::MOV(Eb,Gb); 0x1: Inst::MOV(Ev,Gv); 0x2: Inst::MOV(Gb,Eb); - 0x3: Inst::MOV(Gv,Eb); + 0x3: Inst::MOV(Gv,Ev); 0x4: mov_MwRv_Sw(); //What to do with this one? - 0x5: lea_Gv_M(); + 0x5: Inst::LEA(Gv,M); 0x6: mov_Sw_MwRv(); 0x7: group10_Ev(); //Make sure this is Ev } 0x12: decode OPCODE_OP_BOTTOM3 { - 0x0: nop_or_pause(); //Check for repe prefix + default: nop_or_pause(); //Check for repe prefix 0x1: xchg_rCX_rAX(); 0x2: xchg_rDX_rAX(); 0x3: xchg_rVX_rAX(); @@ -269,12 +334,23 @@ 0x13: decode OPCODE_OP_BOTTOM3 { 0x0: cbw_or_cwde_or_cdqe_rAX(); 0x1: cwd_or_cdq_or_cqo_rAX_rDX(); - 0x2: call_Ap(); + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: call_Ap(); + } 0x3: fwait(); //aka wait 0x4: pushf_Fv(); 0x5: popf_Fv(); - 0x6: sahf(); - 0x7: lahf(); + //Both of these should be illegal only if CPUID.AHF64=0, + //according to sandpile.org + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: sahf(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: lahf(); + } } 0x14: decode OPCODE_OP_BOTTOM3 { 0x0: mov_Al_Ob(); @@ -287,8 +363,8 @@ 0x7: cmps_Yv_Xv(); } 0x15: decode OPCODE_OP_BOTTOM3 { - 0x0: test_Al_Ib(); - 0x1: test_rAX_Iz(); + 0x0: Inst::TEST(rAl,Ib); + 0x1: Inst::TEST(rAX,Iz); 0x2: stos_Yb_Al(); 0x3: stos_Yv_rAX(); 0x4: lods_Al_Xb(); @@ -306,23 +382,31 @@ 0x6: mov_Dh_Ib(); 0x7: mov_Bh_Ib(); } - 0x17: decode OPCODE_OP_BOTTOM3 { - 0x0: mov_rAX_Iv(); - 0x1: mov_rCX_Iv(); - 0x2: mov_rDX_Iv(); - 0x3: mov_rBX_Iv(); - 0x4: mov_rSP_Iv(); - 0x5: mov_rBP_Iv(); - 0x6: mov_rSI_Iv(); - 0x7: mov_rDI_Iv(); + format Inst { + 0x17: decode OPCODE_OP_BOTTOM3 { + 0x0: MOV(rAX,Iv); + 0x1: MOV(rCX,Iv); + 0x2: MOV(rDX,Iv); + 0x3: MOV(rBX,Iv); + 0x4: MOV(rSP,Iv); + 0x5: MOV(rBP,Iv); + 0x6: MOV(rSI,Iv); + 0x7: MOV(rDI,Iv); + } } 0x18: decode OPCODE_OP_BOTTOM3 { 0x0: group2_Eb_Ib(); 0x1: group2_Ev_Ib(); 0x2: ret_near_Iw(); 0x3: ret_near(); - 0x4: les_Gz_Mp(); - 0x5: lds_Gz_Mp(); + 0x4: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: les_Gz_Mp(); + } + 0x5: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: lds_Gz_Mp(); + } //0x6: group12_Eb_Ib(); 0x6: decode MODRM_REG { 0x0: Inst::MOV(Eb,Ib); @@ -339,7 +423,10 @@ 0x3: ret_far(); 0x4: int3(); 0x5: int_Ib(); - 0x6: into(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: into(); + } 0x7: iret(); } 0x1A: decode OPCODE_OP_BOTTOM3 { @@ -347,9 +434,18 @@ 0x1: group2_Ev_1(); 0x2: group2_Eb_Cl(); 0x3: group2_Ev_Cl(); - 0x4: aam_Ib(); - 0x5: aad_Ib(); - 0x6: salc(); + 0x4: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aam_Ib(); + } + 0x5: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aad_Ib(); + } + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: salc(); + } 0x7: xlat(); } 0x1B: decode OPCODE_OP_BOTTOM3 { @@ -373,9 +469,12 @@ 0x7: out_Ib_eAX(); } 0x1D: decode OPCODE_OP_BOTTOM3 { - 0x0: call_Jz(); + 0x0: Inst::CALL(Jz); 0x1: jmp_Jz(); - 0x2: jmp_Ap(); + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: jmp_Ap(); + } 0x3: jmp_Jb(); 0x4: in_Al_Dx(); 0x5: in_eAX_Dx(); diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 37b28fe64..97777f727 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -70,8 +70,8 @@ def format Inst(*opTypeSet) {{ def format MultiInst(switchVal, *opTypeSets) {{ switcher = {} for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets): - switcher[count] = (Name, opTypeSet, EmulEnv()) - blocks = doSplitDecode(specializeInst, switchVal, switcher) + switcher[count] = (specializeInst, Name, opTypeSet, EmulEnv()) + blocks = doSplitDecode(switchVal, switcher) (header_output, decoder_output, decode_block, exec_output) = blocks.makeList() }}; diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 8bb282150..3ef204850 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -96,7 +96,7 @@ output header {{ #include <sstream> #include <iostream> -#include "arch/x86/faults.hh" +#include "arch/x86/emulenv.hh" #include "arch/x86/isa_traits.hh" #include "arch/x86/regfile.hh" #include "arch/x86/types.hh" @@ -104,10 +104,12 @@ output header {{ #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "mem/request.hh" // some constructors use MemReq flags +#include "sim/faults.hh" }}; output decoder {{ - +#include "arch/x86/faults.hh" +#include "arch/x86/segmentregs.hh" #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py index 283152f30..809b9ac7c 100644 --- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -53,7 +53,27 @@ # # Authors: Gabe Black -microcode = "" +microcode = ''' +def macroop SUB_R_I +{ + subi reg, reg, imm +}; + +def macroop SUB_M_I +{ + ld t1, ds, [scale, index, base], disp + subi t1, t1, imm + st t1, ds, [scale, index, base], disp +}; + +def macroop SUB_P_I +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + subi t1, t1, imm + st t1, ds, [scale, index, base], disp +}; +''' #let {{ # class ADC(Inst): # "Adc ^0 ^0 ^1" diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py index b4d1cf9b8..89d406912 100644 --- a/src/arch/x86/isa/insts/compare_and_test/test.py +++ b/src/arch/x86/isa/insts/compare_and_test/test.py @@ -53,8 +53,43 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class TEST(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop TEST_M_R +{ + ld t1, ds, [scale, index, base], disp + and t0, t1, reg +}; + +def macroop TEST_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + and t0, t1, reg +}; + +def macroop TEST_R_R +{ + and t0, reg, regm +}; + +def macroop TEST_M_I +{ + ld t1, ds, [scale, index, base], disp + limm t2, imm + and t0, t1, t2 +}; + +def macroop TEST_P_I +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + limm t2, imm + and t0, t1, t2 +}; + +def macroop TEST_R_I +{ + limm t1, imm + and t0, reg, t1 +}; +''' diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py index 231db6e40..1372f7dba 100644 --- a/src/arch/x86/isa/insts/control_transfer/call.py +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -53,7 +53,19 @@ # # Authors: Gabe Black -microcode = "" +microcode = ''' +def macroop CALL_I +{ + # Make the default data size of pops 64 bits in 64 bit mode + .adjust_env oszIn64Override + + limm t2, imm + rdip t1 + subi "INTREG_RSP", "INTREG_RSP", dsz + st t1, ss, [0, t0, "INTREG_RSP"] + wrip t1, t2 +}; +''' #let {{ # class CALL(Inst): # "GenFault ${new UnimpInstFault}" diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py index ff4af0af4..c85dd7cc4 100644 --- a/src/arch/x86/isa/insts/data_transfer/move.py +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -55,24 +55,55 @@ microcode = ''' def macroop MOV_R_R { - mov "env.reg", "env.reg", "env.regm" + mov reg, reg, regm }; def macroop MOV_M_R { - #Do a store to put the register operand into memory + st reg, ds, [scale, index, base], disp +}; + +def macroop MOV_P_R { + rdip t7 + st reg, ds, [scale, index, base], disp }; def macroop MOV_R_M { - #Do a load to fill the register operand from memory + ld reg, ds, [scale, index, base], disp +}; + +def macroop MOV_R_P { + rdip t7 + ld reg, ds, [scale, index, base], disp }; def macroop MOV_R_I { - limm "env.reg", "IMMEDIATE" + limm reg, imm }; def macroop MOV_M_I { - limm "env.reg", "IMMEDIATE" - #Do a store to put the register operand into memory + limm t1, imm + st t1, ds, [scale, index, base], disp +}; + +def macroop MOV_P_I { + rdip t7 + limm t1, imm + st t1, ds, [scale, index, base], disp +}; + +def macroop MOVSXD_R_R { + sext reg, regm, dsz +}; + +def macroop MOVSXD_R_M { + ld t1, ds, [scale, index, base], disp + sext reg, t1, dsz +}; + +def macroop MOVSXD_R_P { + rdip t7 + ld t1, ds, [scale, index, base], disp + sext reg, t1, dsz }; ''' #let {{ diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py index 50b690354..ca2443752 100644 --- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -55,34 +55,26 @@ microcode = ''' def macroop POP_R { - # Make the default data size of pops 64 bits in 64 bit mode - .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + .adjust_env oszIn64Override - ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] - addi "INTREG_RSP", "INTREG_RSP", "env.dataSize" + ld reg, ss, [0, t0, "INTREG_RSP"] + addi "INTREG_RSP", "INTREG_RSP", dsz }; def macroop PUSH_R { - # Make the default data size of pops 64 bits in 64 bit mode - .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + .adjust_env oszIn64Override - subi "INTREG_RSP", "INTREG_RSP", "env.dataSize" - st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] + subi "INTREG_RSP", "INTREG_RSP", dsz + st reg, ss, [0, t0, "INTREG_RSP"] }; ''' #let {{ -# class POP(Inst): -# "GenFault ${new UnimpInstFault}" -# class POPA(Inst): -# "GenFault ${new UnimpInstFault}" # class POPA(Inst): # "GenFault ${new UnimpInstFault}" # class POPAD(Inst): # "GenFault ${new UnimpInstFault}" -# class PUSH(Inst): -# "GenFault ${new UnimpInstFault}" # class PUSHA(Inst): # "GenFault ${new UnimpInstFault}" # class PUSHAD(Inst): diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py index dab6960b1..dcaf9778e 100644 --- a/src/arch/x86/isa/insts/load_effective_address.py +++ b/src/arch/x86/isa/insts/load_effective_address.py @@ -53,8 +53,13 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class LEA(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop LEA_R_M { + lea reg, ds, [scale, index, base], disp +}; + +def macroop LEA_R_P { + rdip t7 + lea reg, ds, [scale, index, base], disp +}; +''' diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py index 824c75053..2fd369d60 100644 --- a/src/arch/x86/isa/insts/logical.py +++ b/src/arch/x86/isa/insts/logical.py @@ -56,56 +56,72 @@ microcode = ''' def macroop XOR_R_R { - xor "env.reg", "env.reg", "env.regm" + xor reg, reg, regm }; def macroop XOR_R_I { - limm "NUM_INTREGS+1", "IMMEDIATE" - xor "env.reg", "env.reg", "NUM_INTREGS+1" + limm t1, imm + xor reg, reg, t1 }; def macroop XOR_M_R { - #Do a load to get one of the sources - xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg" - #Do a store to write the destination + ld t1, ds, [scale, index, base], disp + xor t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop XOR_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + xor t1, t1, reg + st t1, ds, [scale, index, base], disp }; def macroop XOR_R_M { - #Do a load to get one of the sources - xor "env.reg", "env.reg", "NUM_INTREGS+1" + ld t1, ds, [scale, index, base], disp + xor reg, reg, t1 +}; + +def macroop XOR_R_P +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + xor reg, reg, t1 }; def macroop AND_R_I { - limm "NUM_INTREGS+1", "IMMEDIATE" - and "env.reg", "env.reg", "NUM_INTREGS+1" + limm t1, imm + and reg, reg, t1 }; def macroop AND_M_I { - #Do a load to get one of the sources - limm "NUM_INTREGS+1", "IMMEDIATE" - and "NUM_INTREGS+1", "NUM_INTREGS+1", "NUM_INTREGS+2" - #Do a store to write the destination + ld t2, ds, [scale, index, base], disp + limm t1, imm + and t2, t2, t1 + st t2, ds, [scale, index, base], disp +}; + +def macroop AND_P_I +{ + rdip t7 + ld t2, ds, [scale, index, base], disp + limm t1, imm + and t2, t2, t1 + st t2, ds, [scale, index, base], disp }; ''' #let {{ #microcodeString = ''' -# def macroop AND -# { -# And reg reg regm -# }; # def macroop OR # { # Or reg reg regm # }; -# def macroop XOR -# { -# Xor reg reg regm -# }; # def macroop NOT # { # Xor reg reg "0xFFFFFFFFFFFFFFFFULL" diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 0cc818409..8453a4fe9 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -111,6 +111,12 @@ output header {{ }; }}; +////////////////////////////////////////////////////////////////////////////// +// +// X86 specific +// +////////////////////////////////////////////////////////////////////////////// + // Basic instruction class declaration template. def template MacroDeclare {{ namespace X86Macroop @@ -122,17 +128,19 @@ def template MacroDeclare {{ { public: // Constructor. - %(class_name)s(ExtMachInst machInst, EmulEnv env); + %(class_name)s(ExtMachInst machInst, X86ISA::EmulEnv env); }; }; }}; // Basic instruction class constructor template. def template MacroConstructor {{ - inline X86Macroop::%(class_name)s::%(class_name)s(ExtMachInst machInst, EmulEnv env) + inline X86Macroop::%(class_name)s::%(class_name)s( + ExtMachInst machInst, EmulEnv env) : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { %(adjust_env)s; + %(do_modrm)s; %(constructor)s; //alloc_microops is the code that sets up the microops //array in the parent class. @@ -140,11 +148,6 @@ def template MacroConstructor {{ } }}; -////////////////////////////////////////////////////////////////////////////// -// -// X86 specific -// - let {{ from micro_asm import Combinational_Macroop, Rom_Macroop class X86Macroop(Combinational_Macroop): @@ -157,6 +160,7 @@ let {{ } self.declared = False self.adjust_env = "" + self.doModRM = "" def getAllocator(self, env): return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) def getDeclaration(self): @@ -180,31 +184,11 @@ let {{ iop = InstObjParams(self.name, self.name, "Macroop", {"code" : "", "num_microops" : numMicroops, "alloc_microops" : allocMicroops, - "adjust_env" : self.adjust_env}) + "adjust_env" : self.adjust_env, + "do_modrm" : self.doModRM}) return MacroConstructor.subst(iop); }}; -output header {{ - struct EmulEnv - { - X86ISA::RegIndex reg; - X86ISA::RegIndex regm; - uint8_t scale; - X86ISA::RegIndex index; - X86ISA::RegIndex base; - int dataSize; - int addressSize; - int stackSize; - - EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm, - int _dataSize, int _addressSize, int _stackSize) : - reg(_reg), regm(_regm), - dataSize(_dataSize), addressSize(_addressSize), - stackSize(_stackSize) - {;} - }; -}}; - let {{ class EmulEnv(object): def __init__(self): @@ -215,6 +199,8 @@ let {{ self.addressSize = "ADDRSIZE" self.dataSize = "OPSIZE" self.stackSize = "STACKSIZE" + self.doModRM = False + def getAllocator(self): return '''EmulEnv(%(reg)s, %(regm)s, @@ -234,12 +220,15 @@ let {{ }}; let {{ + doModRMString = "env.doModRM(machInst);\n" def genMacroop(Name, env): blocks = OutputBlocks() if not macroopDict.has_key(Name): raise Exception, "Unrecognized instruction: %s" % Name macroop = macroopDict[Name] if not macroop.declared: + if env.doModRM: + macroop.doModRM = doModRMString blocks.header_output = macroop.getDeclaration() blocks.decoder_output = macroop.getDefinition() macroop.declared = True diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index fde430691..4e06f4391 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -68,9 +68,37 @@ let {{ import sys sys.path[0:0] = ["src/arch/x86/isa/"] from insts import microcode - print microcode + # print microcode from micro_asm import MicroAssembler, Rom_Macroop, Rom mainRom = Rom('main ROM') assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop) + # Add in symbols for the microcode registers + for num in range(15): + assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num + # Add in symbols for the segment descriptor registers + for letter in ("C", "D", "E", "F", "G", "S"): + assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter + # Miscellaneous symbols + symbols = { + "reg" : "env.reg", + "regm" : "env.regm", + "imm" : "IMMEDIATE", + "disp" : "DISPLACEMENT", + "scale" : "env.scale", + "index" : "env.index", + "base" : "env.base", + "dsz" : "env.dataSize", + "osz" : "env.operandSize", + "ssz" : "env.stackSize" + } + assembler.symbols.update(symbols) + + # Code literal which forces a default 64 bit operand size in 64 bit mode. + assembler.symbols["oszIn64Override"] = ''' + if (machInst.mode.submode == SixtyFourBitMode && + env.dataSize == 4) + env.dataSize = 8; + ''' + macroopDict = assembler.assemble(microcode) }}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 38b690e6a..fbff899a0 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -59,9 +59,6 @@ // ////////////////////////////////////////////////////////////////////////// - -// Load templates - output header {{ /** * Base class for load and store ops @@ -119,6 +116,58 @@ output decoder {{ } }}; +// LEA template + +def template MicroLeaExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + Addr EA; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + %(code)s; + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +def template MicroLeaDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(BasicExecDeclare)s + }; +}}; + +// Load templates + def template MicroLoadExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const @@ -411,13 +460,27 @@ let {{ exec_output += MicroStoreCompleteAcc.subst(iop) class StoreOp(LdStOp): - def __init__(self, data, addr, segment): - super(LoadOp, self).__init__(data, addr, segment) + def __init__(self, data, segment, addr, disp = 0): + super(LoadOp, self).__init__(data, segment, addr, disp) self.className = Name self.mnemonic = name microopClasses[name] = StoreOp defineMicroLoadOp('St', 'Mem = Data;') + + iop = InstObjParams("lea", "Lea", 'LdStOp', + {"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA}) + header_output += MicroLeaDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLeaExecute.subst(iop) + + class LeaOp(LdStOp): + def __init__(self, data, segment, addr, disp = 0): + super(LeaOp, self).__init__(data, segment, addr, disp) + self.className = "Lea" + self.mnemonic = "lea" + + microopClasses["lea"] = LeaOp }}; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index d5fb25cb5..65b75fab8 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -162,6 +162,7 @@ def template MicroRegOpExecute {{ %(op_decl)s; %(op_rd)s; %(code)s; + %(flag_code)s; //Write the resulting state to the execution context if(fault == NoFault) @@ -181,6 +182,7 @@ def template MicroRegOpImmExecute {{ %(op_decl)s; %(op_rd)s; %(code)s; + %(flag_code)s; //Write the resulting state to the execution context if(fault == NoFault) @@ -304,11 +306,11 @@ def template MicroRegOpImmConstructor {{ let {{ class RegOp(X86Microop): - def __init__(self, dest, src1, src2): + def __init__(self, dest, src1, src2, setStatus): self.dest = dest self.src1 = src1 self.src2 = src2 - self.setStatus = False + self.setStatus = setStatus self.dataSize = "env.dataSize" self.ext = 0 @@ -326,11 +328,11 @@ let {{ return allocator class RegOpImm(X86Microop): - def __init__(self, dest, src1, imm8): + def __init__(self, dest, src1, imm8, setStatus): self.dest = dest self.src1 = src1 self.imm8 = imm8 - self.setStatus = False + self.setStatus = setStatus self.dataSize = "env.dataSize" self.ext = 0 @@ -356,11 +358,22 @@ let {{ decoder_output = "" exec_output = "" - def defineMicroRegOp(mnemonic, code): + def setUpMicroRegOp(name, Name, base, code, child, flagCode): global header_output global decoder_output global exec_output global microopClasses + + iop = InstObjParams(name, Name, base, + {"code" : code, + "flag_code" : flagCode}) + header_output += MicroRegOpDeclare.subst(iop) + decoder_output += MicroRegOpConstructor.subst(iop) + exec_output += MicroRegOpExecute.subst(iop) + + microopClasses[name] = child + + def defineMicroRegOp(mnemonic, code, flagCode): Name = mnemonic name = mnemonic.lower() @@ -371,43 +384,96 @@ let {{ regCode = matcher.sub("SrcReg2", code) immCode = matcher.sub("imm8", code) - # Build up the all register version of this micro op - iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode}) - header_output += MicroRegOpDeclare.subst(iop) - decoder_output += MicroRegOpConstructor.subst(iop) - exec_output += MicroRegOpExecute.subst(iop) - + # Build the all register version of this micro op class RegOpChild(RegOp): - def __init__(self, dest, src1, src2): - super(RegOpChild, self).__init__(dest, src1, src2) + def __init__(self, dest, src1, src2, setStatus=False): + super(RegOpChild, self).__init__(dest, src1, src2, setStatus) self.className = Name self.mnemonic = name - microopClasses[name] = RegOpChild + setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode); + + # Build the immediate version of this micro op + class RegOpChildImm(RegOpImm): + def __init__(self, dest, src1, src2, setStatus=False): + super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus) + self.className = Name + "Imm" + self.mnemonic = name + "i" + + setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode); - # Build up the immediate version of this micro op - iop = InstObjParams(name + "i", Name, - 'RegOpImm', {"code" : immCode}) - header_output += MicroRegOpImmDeclare.subst(iop) - decoder_output += MicroRegOpImmConstructor.subst(iop) - exec_output += MicroRegOpImmExecute.subst(iop) + defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF + defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "") + defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF + defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF + defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "") + defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF + defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "") + defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg + defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "") + + # This has it's own function because Wr ops have implicit destinations + def defineMicroRegOpWr(mnemonic, code): + Name = mnemonic + name = mnemonic.lower() - class RegOpImmChild(RegOpImm): - def __init__(self, dest, src1, imm): - super(RegOpImmChild, self).__init__(dest, src1, imm) + # Find op2 in each of the instruction definitions. Create two versions + # of the code, one with an integer operand, and one with an immediate + # operand. + matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") + regCode = matcher.sub("SrcReg2", code) + immCode = matcher.sub("imm8", code) + + # Build the all register version of this micro op + class RegOpChild(RegOp): + def __init__(self, src1, src2): + super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False) + self.className = Name + self.mnemonic = name + + setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, ""); + + # Build the immediate version of this micro op + class RegOpChildImm(RegOpImm): + def __init__(self, src1, src2): + super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False) self.className = Name + "Imm" self.mnemonic = name + "i" - microopClasses[name + "i"] = RegOpImmChild + setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, ""); + + defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') + + # This has it's own function because Rd ops don't always have two parameters + def defineMicroRegOpRd(mnemonic, code): + Name = mnemonic + name = mnemonic.lower() + + class RegOpChild(RegOp): + def __init__(self, dest, src1 = "NUM_INTREGS"): + super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False) + self.className = Name + self.mnemonic = name + + setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, ""); + + defineMicroRegOpRd('Rdip', 'DestReg = RIP') + + def defineMicroRegOpImm(mnemonic, code): + Name = mnemonic + name = mnemonic.lower() + + class RegOpChild(RegOpImm): + def __init__(self, dest, src1, src2): + super(RegOpChild, self).__init__(dest, src1, src2, False) + self.className = Name + self.mnemonic = name - defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF - defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') - defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF - defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF - defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') - defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF - defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') - defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg - defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') + setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, ""); + defineMicroRegOpImm('Sext', ''' + IntReg val = SrcReg1; + int sign_bit = bits(val, imm8-1, imm8-1); + val = sign_bit ? (val | ~mask(imm8)) : val; + DestReg = merge(DestReg, val, dataSize);''') }}; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 96fdf1c5e..b56223390 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -59,67 +59,63 @@ // ////////////////////////////////////////////////////////////////////////// -def template MicroFaultExecute {{ - Fault %(class_name)s ::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - //Return the fault we were constructed with - return fault; - } -}}; - -def template MicroFaultDeclare {{ - class %(class_name)s : public X86MicroopBase +output header {{ + class MicroFault : public X86MicroopBase { protected: Fault fault; void buildMe(); public: - %(class_name)s(ExtMachInst _machInst, - const char * instMnem, + MicroFault(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, Fault _fault); - %(class_name)s(ExtMachInst _machInst, - const char * instMnem, + MicroFault(ExtMachInst _machInst, const char * instMnem, Fault _fault); %(BasicExecDeclare)s }; }}; -def template MicroFaultConstructor {{ - - inline void %(class_name)s::buildMe() - { - %(constructor)s; - } +output decoder {{ + Fault MicroFault::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + //Return the fault we were constructed with + return fault; + } +}}; - inline %(class_name)s::%(class_name)s( +output decoder {{ + inline MicroFault::MicroFault( ExtMachInst machInst, const char * instMnem, Fault _fault) : - %(base_class)s(machInst, "%(mnemonic)s", instMnem, - false, false, false, false, %(op_class)s), fault(_fault) + X86MicroopBase(machInst, "fault", instMnem, + false, false, false, false, No_OpClass), fault(_fault) { - buildMe(); } - inline %(class_name)s::%(class_name)s( + inline MicroFault::MicroFault( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, Fault _fault) : - %(base_class)s(machInst, "%(mnemonic)s", instMnem, - isMicro, isDelayed, isFirst, isLast, %(op_class)s), + X86MicroopBase(machInst, "fault", instMnem, + isMicro, isDelayed, isFirst, isLast, No_OpClass), fault(_fault) { - buildMe(); } }}; let {{ - # This microop takes in a single parameter, a fault to return. - iop = InstObjParams("fault", "GenFault", 'X86MicroopBase', {"code" : ""}) - header_output += MicroFaultDeclare.subst(iop) - decoder_output += MicroFaultConstructor.subst(iop) - exec_output += MicroFaultExecute.subst(iop) + class Fault(X86Microop): + def __init__(self, fault): + self.fault = fault + + def getAllocator(self, *microFlags): + allocator = '''new MicroFault(machInst, mnemonic + %(flags)s, %(fault)s)''' % { + "flags" : self.microFlagsText(microFlags), + "fault" : self.fault} + return allocator + microopClasses["fault"] = Fault }}; diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index bb2be47d9..3183f32ba 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -64,18 +64,18 @@ let {{ # This code builds up a decode block which decodes based on switchval. # vals is a dict which matches case values with what should be decoded to. - # builder is called on the exploded contents of "vals" values to generate - # whatever code should be used. - def doSplitDecode(builder, switchVal, vals, default = None): + # Each element of the dict is a list containing a function and then the + # arguments to pass to it. + def doSplitDecode(switchVal, vals, default = None): blocks = OutputBlocks() blocks.decode_block = 'switch(%s) {\n' % switchVal for (val, todo) in vals.items(): - new_blocks = builder(*todo) + new_blocks = todo[0](*todo[1:]) new_blocks.decode_block = \ '\tcase %s: %s\n' % (val, new_blocks.decode_block) blocks.append(new_blocks) if default: - new_blocks = builder(*default) + new_blocks = default[0](*default[1:]) new_blocks.decode_block = \ '\tdefault: %s\n' % new_blocks.decode_block blocks.append(new_blocks) @@ -84,8 +84,29 @@ let {{ }}; let {{ + def doRipRelativeDecode(Name, opTypes, env): + # print "RIPing %s with opTypes %s" % (Name, opTypes) + normBlocks = specializeInst(Name + "_M", copy.copy(opTypes), copy.copy(env)) + ripBlocks = specializeInst(Name + "_P", copy.copy(opTypes), copy.copy(env)) + + blocks = OutputBlocks() + blocks.append(normBlocks) + blocks.append(ripBlocks) + + blocks.decode_block = ''' + if(machInst.modRM.mod == 0 && + machInst.modRM.rm == 5 && + machInst.mode.submode == SixtyFourBitMode) + { %s } + else + { %s }''' % \ + (ripBlocks.decode_block, normBlocks.decode_block) + return blocks +}}; + +let {{ class OpType(object): - parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Z0-9]*)(?P<rsize>[a-z]*))") + parser = re.compile(r"(?P<tag>[A-Z]+)(?P<size>[a-z]*)|(r(?P<reg>[A-Z0-9]+)(?P<rsize>[a-z]*))") def __init__(self, opTypeString): match = OpType.parser.search(opTypeString) if match == None: @@ -105,14 +126,15 @@ let {{ while len(opTypes): # Parse the operand type string we're working with opType = OpType(opTypes[0]) + opTypes.pop(0) if opType.reg: #Figure out what to do with fixed register operands #This is the index to use, so we should stick it some place. if opType.reg in ("A", "B", "C", "D"): - env.addReg("INTREG_R%sX" % opType.reg) + env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg) else: - env.addReg("INTREG_R%s" % opType.reg) + env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg) if opType.size: if opType.rsize in ("l", "h", "b"): print "byte" @@ -121,6 +143,11 @@ let {{ else: print "Didn't recognize fixed register size %s!" % opType.rsize Name += "_R" + elif opType.tag == "M": + # This refers to memory. The macroop constructor sets up modrm + # addressing. Non memory modrm settings should cause an error. + Name += "_M" + env.doModRM = True elif opType.tag == None or opType.size == None: raise Exception, "Problem parsing operand tag: %s" % opType.tag elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"): @@ -130,39 +157,24 @@ let {{ elif opType.tag in ("E", "Q", "W"): # This might refer to memory or to a register. We need to # divide it up farther. - regTypes = copy.copy(opTypes) - regTypes.pop(0) regEnv = copy.copy(env) regEnv.addReg(ModRMRMIndex) - regName = Name + "_R" - # This needs to refer to memory, but we'll fill in the details - # later. It needs to take into account unaligned memory - # addresses. - memTypes = copy.copy(opTypes) - memTypes.pop(0) + # This refers to memory. The macroop constructor should set up + # modrm addressing. memEnv = copy.copy(env) - memName = Name + "_M" - print "%0" - return doSplitDecode(specializeInst, "MODRM_MOD", - {"3" : (regName, regTypes, regEnv)}, - (memName, memTypes, memEnv)) + memEnv.doModRM = True + return doSplitDecode("MODRM_MOD", + {"3" : (specializeInst, Name + "_R", copy.copy(opTypes), regEnv)}, + (doRipRelativeDecode, Name, copy.copy(opTypes), memEnv)) elif opType.tag in ("I", "J"): # Immediates Name += "_I" - elif opType.tag == "M": - # This needs to refer to memory, but we'll fill in the details - # later. It needs to take into account unaligned memory - # addresses. - print "%0" - Name += "_M" elif opType.tag in ("PR", "R", "VR"): - # There should probably be a check here to verify that mod - # is equal to 11b + # Non register modrm settings should cause an error env.addReg(ModRMRMIndex) Name += "_R" else: raise Exception, "Unrecognized tag %s." % opType.tag - opTypes.pop(0) # Generate code to return a macroop of the given name which will # operate in the "emulation environment" env diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc index 3ed18aeb2..49f76699b 100644 --- a/src/arch/x86/predecoder.cc +++ b/src/arch/x86/predecoder.cc @@ -264,31 +264,30 @@ namespace X86ISA Predecoder::State Predecoder::doModRMState(uint8_t nextByte) { State nextState = ErrorState; - emi.modRM = nextByte; + ModRM modRM; + modRM = nextByte; DPRINTF(Predecoder, "Found modrm byte %#x.\n", nextByte); if (0) {//FIXME in 16 bit mode //figure out 16 bit displacement size - if(nextByte & 0xC7 == 0x06 || - nextByte & 0xC0 == 0x80) + if(modRM.mod == 0 && modRM.rm == 6 || modRM.mod == 2) displacementSize = 2; - else if(nextByte & 0xC0 == 0x40) + else if(modRM.mod == 1) displacementSize = 1; else displacementSize = 0; } else { //figure out 32/64 bit displacement size - if(nextByte & 0xC6 == 0x04 || - nextByte & 0xC0 == 0x80) + if(modRM.mod == 0 && (modRM.rm == 4 || modRM.rm == 5) + || modRM.mod == 2) displacementSize = 4; - else if(nextByte & 0xC0 == 0x40) + else if(modRM.mod == 1) displacementSize = 1; else displacementSize = 0; } //If there's an SIB, get that next. //There is no SIB in 16 bit mode. - if(nextByte & 0x7 == 4 && - nextByte & 0xC0 != 0xC0) { + if(modRM.rm == 4 && modRM.mod != 3) { // && in 32/64 bit mode) nextState = SIBState; } else if(displacementSize) { @@ -301,6 +300,7 @@ namespace X86ISA } //The ModRM byte is consumed no matter what consumeByte(); + emi.modRM = modRM; return nextState; } diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 3c858f061..f34b66364 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -195,12 +195,12 @@ namespace X86ISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data) + void moreBytes(Addr pc, Addr fetchPC, MachInst data) { + DPRINTF(Predecoder, "Getting more bytes.\n"); basePC = fetchPC; - offset = off; + offset = (fetchPC >= pc) ? 0 : pc - fetchPC; fetchChunk = data; - assert(off < sizeof(MachInst)); outOfBytes = false; process(); } diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index af7494598..7deb54945 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -268,7 +268,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) int argv_array_size = intSize * (argv.size() + 1); int argc_size = intSize; - int window_save_size = intSize * 16; int space_needed = mysterious_size + @@ -276,8 +275,7 @@ X86LiveProcess::argsInit(int intSize, int pageSize) aux_array_size + envp_array_size + argv_array_size + - argc_size + - window_save_size; + argc_size; stack_min = stack_base - space_needed; stack_min &= alignmentMask; @@ -296,10 +294,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) Addr envp_array_base = auxv_array_base - envp_array_size; Addr argv_array_base = envp_array_base - argv_array_size; Addr argc_base = argv_array_base - argc_size; -#ifndef NDEBUG - // only used in DPRINTF - Addr window_save_base = argc_base - window_save_size; -#endif DPRINTF(X86, "The addresses of items on the initial stack:\n"); DPRINTF(X86, "0x%x - file name\n", file_name_base); @@ -309,7 +303,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) DPRINTF(X86, "0x%x - envp array\n", envp_array_base); DPRINTF(X86, "0x%x - argv array\n", argv_array_base); DPRINTF(X86, "0x%x - argc \n", argc_base); - DPRINTF(X86, "0x%x - window save\n", window_save_base); DPRINTF(X86, "0x%x - stack min\n", stack_min); // write contents to stack diff --git a/src/arch/x86/segmentregs.hh b/src/arch/x86/segmentregs.hh new file mode 100644 index 000000000..9fd9bcb0e --- /dev/null +++ b/src/arch/x86/segmentregs.hh @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_SEGMENTREGS_HH__ +#define __ARCH_X86_SEGMENTREGS_HH__ + +namespace X86ISA +{ + enum SegmentRegIndex + { + SEGMENT_REG_ES, + SEGMENT_REG_CS, + SEGMENT_REG_SS, + SEGMENT_REG_DS, + SEGMENT_REG_FS, + SEGMENT_REG_GS, + + NUM_SEGMENTREGS + }; +}; + +#endif // __ARCH_X86_SEGMENTREGS_HH__ diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 298dff80b..61ab2bac9 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -160,7 +160,7 @@ namespace X86ISA } opcode; //Modifier bytes ModRM modRM; - uint8_t sib; + Sib sib; //Immediate fields uint64_t immediate; uint64_t displacement; |