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-rw-r--r--src/arch/x86/intmessage.hh3
-rw-r--r--src/arch/x86/pagetable_walker.cc4
-rw-r--r--src/arch/x86/pagetable_walker.hh16
3 files changed, 16 insertions, 7 deletions
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index f4a3ab9a6..4a165a4a1 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -80,7 +80,8 @@ namespace X86ISA
prepIntRequest(const uint8_t id, Addr offset, Addr size)
{
RequestPtr req = new Request(x86InterruptAddress(id, offset),
- size, Request::UNCACHEABLE);
+ size, Request::UNCACHEABLE,
+ Request::intMasterId);
PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
pkt->allocate();
return pkt;
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 5b1730f0c..f29531cd5 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -499,7 +499,7 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
Request::Flags flags = oldRead->req->getFlags();
flags.set(Request::UNCACHEABLE, uncacheable);
RequestPtr request =
- new Request(nextRead, oldRead->getSize(), flags);
+ new Request(nextRead, oldRead->getSize(), flags, walker->masterId);
read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
read->allocate();
// If we need to write, adjust the read packet to write the modified
@@ -569,7 +569,7 @@ Walker::WalkerState::setupWalk(Addr vaddr)
Request::Flags flags = Request::PHYSICAL;
if (cr3.pcd)
flags.set(Request::UNCACHEABLE);
- RequestPtr request = new Request(topAddr, dataSize, flags);
+ RequestPtr request = new Request(topAddr, dataSize, flags, walker->masterId);
read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
read->allocate();
}
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index 73e185148..d433c7b98 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -50,6 +50,7 @@
#include "mem/packet.hh"
#include "params/X86PagetableWalker.hh"
#include "sim/faults.hh"
+#include "sim/system.hh"
class ThreadContext;
@@ -67,7 +68,7 @@ namespace X86ISA
{}
protected:
- Walker * walker;
+ Walker *walker;
bool recvTiming(PacketPtr pkt);
Tick recvAtomic(PacketPtr pkt);
@@ -97,7 +98,7 @@ namespace X86ISA
};
protected:
- Walker * walker;
+ Walker *walker;
ThreadContext *tc;
RequestPtr req;
State state;
@@ -115,7 +116,6 @@ namespace X86ISA
bool timing;
bool retrying;
bool started;
-
public:
WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
RequestPtr _req, bool _isFunctional = false) :
@@ -172,6 +172,7 @@ namespace X86ISA
// The TLB we're supposed to load.
TLB * tlb;
System * sys;
+ MasterID masterId;
// Functions for dealing with packets.
bool recvTiming(PacketPtr pkt);
@@ -187,9 +188,16 @@ namespace X86ISA
typedef X86PagetableWalkerParams Params;
+ const Params *
+ params() const
+ {
+ return static_cast<const Params *>(_params);
+ }
+
Walker(const Params *params) :
MemObject(params), port(name() + ".port", this),
- funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system)
+ funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
+ masterId(sys->getMasterId(name()))
{
}
};