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-rw-r--r--src/arch/x86/isa.cc12
-rw-r--r--src/arch/x86/remote_gdb.cc3
-rw-r--r--src/arch/x86/tlb.cc7
-rw-r--r--src/arch/x86/tlb.hh14
-rw-r--r--src/arch/x86/vtophys.cc2
5 files changed, 15 insertions, 23 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index f092f4418..28c50f358 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -216,8 +216,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
}
}
if (toggled.pg) {
- tc->getITBPtr()->flushAll();
- tc->getDTBPtr()->flushAll();
+ dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
+ dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
}
//This must always be 1.
newCR0.et = 1;
@@ -233,15 +233,15 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
case MISCREG_CR2:
break;
case MISCREG_CR3:
- tc->getITBPtr()->flushNonGlobal();
- tc->getDTBPtr()->flushNonGlobal();
+ dynamic_cast<TLB *>(tc->getITBPtr())->flushNonGlobal();
+ dynamic_cast<TLB *>(tc->getDTBPtr())->flushNonGlobal();
break;
case MISCREG_CR4:
{
CR4 toggled = regVal[miscReg] ^ val;
if (toggled.pae || toggled.pse || toggled.pge) {
- tc->getITBPtr()->flushAll();
- tc->getDTBPtr()->flushAll();
+ dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
+ dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
}
}
break;
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 79613971a..a6fdabd73 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -72,7 +72,8 @@ bool
RemoteGDB::acc(Addr va, size_t len)
{
if (FullSystem) {
- Walker *walker = context->getDTBPtr()->getWalker();
+ Walker *walker = dynamic_cast<TLB *>(
+ context->getDTBPtr())->getWalker();
unsigned logBytes;
Fault fault = walker->startFunctional(context, va, logBytes,
BaseTLB::Read);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index e954c9c73..0b1df9e21 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -440,13 +440,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(fault, req, tc, mode);
}
-Fault
-TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
-{
- panic("Not implemented\n");
- return NoFault;
-}
-
Walker *
TLB::getWalker()
{
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index d036b74d6..c3dc83bb2 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -122,13 +122,11 @@ namespace X86ISA
return ++lruSeq;
}
- Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
- void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, Mode mode);
- /** Stub function for compilation support of CheckerCPU. x86 ISA does
- * not support Checker model at the moment
- */
- Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault translateAtomic(
+ RequestPtr req, ThreadContext *tc, Mode mode) override;
+ void translateTiming(
+ RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode) override;
/**
* Do post-translation physical address finalization.
@@ -144,7 +142,7 @@ namespace X86ISA
* @return A fault on failure, NoFault otherwise.
*/
Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
- Mode mode) const;
+ Mode mode) const override;
TlbEntry * insert(Addr vpn, TlbEntry &entry);
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
index 9b76d89a5..d0287f2ce 100644
--- a/src/arch/x86/vtophys.cc
+++ b/src/arch/x86/vtophys.cc
@@ -60,7 +60,7 @@ namespace X86ISA
Addr
vtophys(ThreadContext *tc, Addr vaddr)
{
- Walker *walker = tc->getDTBPtr()->getWalker();
+ Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker();
unsigned logBytes;
Addr addr = vaddr;
Fault fault = walker->startFunctional(