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-rw-r--r--src/arch/alpha/locked_mem.hh4
-rw-r--r--src/arch/arm/locked_mem.hh4
-rw-r--r--src/arch/generic/locked_mem.hh4
-rw-r--r--src/arch/hsail/insts/mem.hh19
-rw-r--r--src/arch/mips/locked_mem.hh4
-rw-r--r--src/arch/riscv/locked_mem.hh4
6 files changed, 20 insertions, 19 deletions
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 36a6a0333..a71a24cfb 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -85,7 +85,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
xc->setMiscReg(MISCREG_LOCKFLAG, true);
@@ -99,7 +99,7 @@ handleLockedSnoopHit(XC *xc)
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index 2fcbc4a92..d33978522 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -91,7 +91,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
xc->setMiscReg(MISCREG_LOCKFLAG, true);
@@ -111,7 +111,7 @@ handleLockedSnoopHit(XC *xc)
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
if (req->isSwap())
return true;
diff --git a/src/arch/generic/locked_mem.hh b/src/arch/generic/locked_mem.hh
index 68a4ff540..f6537995b 100644
--- a/src/arch/generic/locked_mem.hh
+++ b/src/arch/generic/locked_mem.hh
@@ -63,7 +63,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
}
@@ -76,7 +76,7 @@ handleLockedSnoopHit(XC *xc)
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
return true;
}
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index 36a6cbc79..68a61feea 100644
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -461,9 +461,10 @@ namespace HsailISA
*d = gpuDynInst->wavefront()->ldsChunk->
read<c0>(vaddr);
} else {
- Request *req = new Request(0, vaddr, sizeof(c0), 0,
- gpuDynInst->computeUnit()->masterId(),
- 0, gpuDynInst->wfDynId);
+ RequestPtr req = new Request(0,
+ vaddr, sizeof(c0), 0,
+ gpuDynInst->computeUnit()->masterId(),
+ 0, gpuDynInst->wfDynId);
gpuDynInst->setRequestFlags(req);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
@@ -588,7 +589,7 @@ namespace HsailISA
gpuDynInst->statusBitVector = VectorMask(1);
gpuDynInst->useContinuation = false;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::ACQUIRE);
@@ -1014,7 +1015,7 @@ namespace HsailISA
gpuDynInst->execContinuation = &GPUStaticInst::execSt;
gpuDynInst->useContinuation = true;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::RELEASE);
@@ -1065,7 +1066,7 @@ namespace HsailISA
gpuDynInst->wavefront()->ldsChunk->write<c0>(vaddr,
*d);
} else {
- Request *req =
+ RequestPtr req =
new Request(0, vaddr, sizeof(c0), 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
@@ -1488,7 +1489,7 @@ namespace HsailISA
gpuDynInst->useContinuation = true;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::RELEASE);
@@ -1620,7 +1621,7 @@ namespace HsailISA
"type.\n");
}
} else {
- Request *req =
+ RequestPtr req =
new Request(0, vaddr, sizeof(c0), 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId,
@@ -1675,7 +1676,7 @@ namespace HsailISA
// the acquire completes
gpuDynInst->useContinuation = false;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::ACQUIRE);
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 5c1e60aa1..7fa1642a8 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -75,7 +75,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
xc->setMiscReg(MISCREG_LLFLAG, true);
@@ -92,7 +92,7 @@ handleLockedSnoopHit(XC *xc)
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index 61fbe0de1..1583258a8 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -82,7 +82,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template <class XC> inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
locked_addrs.push(req->getPaddr() & ~0xF);
DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
@@ -94,7 +94,7 @@ handleLockedSnoopHit(XC *xc)
{}
template <class XC> inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
// Normally RISC-V uses zero to indicate success and nonzero to indicate
// failure (right now only 1 is reserved), but in gem5 zero indicates
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 19:10:06 +0000