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-rw-r--r--src/arch/alpha/isa/mem.isa15
-rw-r--r--src/arch/arm/isa/templates/mem.isa36
-rw-r--r--src/arch/arm/isa/templates/misc.isa10
-rw-r--r--src/arch/mips/isa/formats/mem.isa37
-rw-r--r--src/arch/power/isa/formats/mem.isa10
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa9
6 files changed, 11 insertions, 106 deletions
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index efff0eac7..799f910c3 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -354,20 +354,7 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
+ return NoFault;
}
}};
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index ced7a0037..29ef8d007 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -595,23 +595,11 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
+ warn_once("Complete acc isn't called on normal stores in O3.");
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
-
- return fault;
+ return NoFault;
}
}};
@@ -621,23 +609,11 @@ def template NeonStoreCompleteAcc {{
PacketPtr pkt, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
+ warn_once("Complete acc isn't called on normal stores in O3.");
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
-
- return fault;
+ return NoFault;
}
}};
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index f8dac05f8..915dea9b0 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -387,17 +387,11 @@ def template ClrexCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
- return fault;
+ return NoFault;
}
}};
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 411cc5fda..e7dbd8e9b 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -420,42 +420,7 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-
-def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
- %(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
+ return NoFault;
}
}};
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 3bcf0633a..014e4ff5a 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -212,15 +212,7 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
+ return NoFault;
}
}};
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 31efb9cf6..667b9a23a 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -272,15 +272,6 @@ def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
Trace::InstRecord * traceData) const
{
- Fault fault = NoFault;
- %(op_decl)s;
-
- %(op_rd)s;
- %(postacc_code)s;
- if (fault == NoFault)
- {
- %(op_wb)s;
- }
return NoFault;
}
}};