diff options
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/SConscript | 6 | ||||
-rw-r--r-- | src/arch/arm/SConscript | 8 | ||||
-rw-r--r-- | src/arch/mips/SConscript | 2 | ||||
-rw-r--r-- | src/arch/power/SConscript | 2 | ||||
-rw-r--r-- | src/arch/sparc/SConscript | 4 | ||||
-rw-r--r-- | src/arch/x86/SConscript | 10 |
6 files changed, 16 insertions, 16 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript index 34367b274..a8b7f5354 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -126,7 +126,7 @@ isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter) env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) -TraceFlag('IntRegs') -TraceFlag('FloatRegs') -TraceFlag('MiscRegs') +DebugFlag('IntRegs') +DebugFlag('FloatRegs') +DebugFlag('MiscRegs') CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 51aff52f3..a907e52fb 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -65,10 +65,10 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmNativeTrace.py') SimObject('ArmTLB.py') - TraceFlag('Arm') - TraceFlag('TLBVerbose') - TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi") - TraceFlag('Predecoder', "Instructions returned by the predecoder") + DebugFlag('Arm') + DebugFlag('TLBVerbose') + DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") + DebugFlag('Predecoder', "Instructions returned by the predecoder") if env['FULL_SYSTEM']: Source('interrupts.cc') Source('stacktrace.cc') diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 9e0275de7..46c0dd914 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -41,7 +41,7 @@ if env['TARGET_ISA'] == 'mips': Source('dsp.cc') SimObject('MipsTLB.py') - TraceFlag('MipsPRA') + DebugFlag('MipsPRA') if env['FULL_SYSTEM']: SimObject('MipsSystem.py') diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript index 0f264d223..f96f12757 100644 --- a/src/arch/power/SConscript +++ b/src/arch/power/SConscript @@ -45,7 +45,7 @@ if env['TARGET_ISA'] == 'power': Source('utility.cc') SimObject('PowerTLB.py') - TraceFlag('Power') + DebugFlag('Power') if not env['FULL_SYSTEM']: Source('process.cc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index a8babc28f..cc13d56af 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -44,8 +44,8 @@ if env['TARGET_ISA'] == 'sparc': SimObject('SparcNativeTrace.py') SimObject('SparcTLB.py') - TraceFlag('Sparc', "Generic SPARC ISA stuff") - TraceFlag('RegisterWindows', "Register window manipulation") + DebugFlag('Sparc', "Generic SPARC ISA stuff") + DebugFlag('RegisterWindows', "Register window manipulation") if env['FULL_SYSTEM']: SimObject('SparcSystem.py') diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 9cb774647..2742c79e8 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -66,14 +66,14 @@ if env['TARGET_ISA'] == 'x86': SimObject('X86NativeTrace.py') SimObject('X86TLB.py') - TraceFlag('Predecoder', "Predecoder debug output") - TraceFlag('X86', "Generic X86 ISA debugging") + DebugFlag('Predecoder', "Predecoder debug output") + DebugFlag('X86', "Generic X86 ISA debugging") if env['FULL_SYSTEM']: - TraceFlag('LocalApic', "Local APIC debugging") - TraceFlag('PageTableWalker', \ + DebugFlag('LocalApic', "Local APIC debugging") + DebugFlag('PageTableWalker', \ "Page table walker state machine debugging") - TraceFlag('Faults', "Trace all faults/exceptions/traps") + DebugFlag('Faults', "Trace all faults/exceptions/traps") SimObject('X86LocalApic.py') SimObject('X86System.py') |