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-rw-r--r--src/arch/alpha/types.hh3
-rw-r--r--src/arch/mips/types.hh124
-rw-r--r--src/arch/sparc/types.hh4
-rw-r--r--src/arch/x86/types.hh4
4 files changed, 105 insertions, 30 deletions
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index 6433ea3ca..f6648b776 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -70,6 +70,9 @@ namespace AlphaISA
ITOUCH_ANNOTE = 0xffffffff,
};
+ struct CoreSpecific {
+ int core_type;
+ };
} // namespace AlphaISA
#endif
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index 9dea452e6..4208cb2d8 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -1,37 +1,31 @@
/*
- * Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
*
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
*
- * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
- *
- * Authors: Korey L. Sewell
+ * Authors: Korey Sewell
*/
#ifndef __ARCH_MIPS_TYPES_HH__
@@ -101,6 +95,76 @@ namespace MipsISA
RND_NEAREST
};
+struct CoreSpecific {
+ /* Note: It looks like it will be better to allow simulator users
+ to specify the values of individual variables instead of requiring
+ users to define the values of entire registers
+ Especially since a lot of these variables can be created from other
+ user parameters (cache descriptions)
+ -jpp
+ */
+ // MIPS CP0 State - First individual variables
+ // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA)
+ unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
+ unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
+ unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
+ unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
+ unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
+ unsigned CP0_PRId_ProcessorID; // Page 105
+ unsigned CP0_PRId_Revision; // Page 105
+ unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system
+ unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
+ unsigned CP0_Config_AT; //Page 109
+ unsigned CP0_Config_AR; //Page 109
+ unsigned CP0_Config_MT; //Page 109
+ unsigned CP0_Config_VI; //Page 109
+ unsigned CP0_Config1_M; // Page 110
+ unsigned CP0_Config1_MMU; // Page 110
+ unsigned CP0_Config1_IS; // Page 110
+ unsigned CP0_Config1_IL; // Page 111
+ unsigned CP0_Config1_IA; // Page 111
+ unsigned CP0_Config1_DS; // Page 111
+ unsigned CP0_Config1_DL; // Page 112
+ unsigned CP0_Config1_DA; // Page 112
+ bool CP0_Config1_C2; // Page 112
+ bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
+ bool CP0_Config1_PC;// Page 112
+ bool CP0_Config1_WR;// Page 113
+ bool CP0_Config1_CA;// Page 113
+ bool CP0_Config1_EP;// Page 113
+ bool CP0_Config1_FP;// Page 113
+ bool CP0_Config2_M; // Page 114
+ unsigned CP0_Config2_TU;// Page 114
+ unsigned CP0_Config2_TS;// Page 114
+ unsigned CP0_Config2_TL;// Page 115
+ unsigned CP0_Config2_TA;// Page 115
+ unsigned CP0_Config2_SU;// Page 115
+ unsigned CP0_Config2_SS;// Page 115
+ unsigned CP0_Config2_SL;// Page 116
+ unsigned CP0_Config2_SA;// Page 116
+ bool CP0_Config3_M; //// Page 117
+ bool CP0_Config3_DSPP;// Page 117
+ bool CP0_Config3_LPA;// Page 117
+ bool CP0_Config3_VEIC;// Page 118
+ bool CP0_Config3_VInt; // Page 118
+ bool CP0_Config3_SP;// Page 118
+ bool CP0_Config3_MT;// Page 119
+ bool CP0_Config3_SM;// Page 119
+ bool CP0_Config3_TL;// Page 119
+
+ bool CP0_WatchHi_M; // Page 124
+ bool CP0_PerfCtr_M; // Page 130
+ bool CP0_PerfCtr_W; // Page 130
+
+
+ // Then, whole registers
+ unsigned CP0_PRId;
+ unsigned CP0_Config;
+ unsigned CP0_Config1;
+ unsigned CP0_Config2;
+ unsigned CP0_Config3;
+};
+
} // namespace MipsISA
#endif
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index 8bd50b7e8..d19e2a99f 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -60,6 +60,10 @@ namespace SparcISA
typedef int RegContextVal;
typedef uint16_t RegIndex;
+
+ struct CoreSpecific {
+ int core_type;
+ };
}
#endif
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index fd33b8383..90df38d13 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -258,6 +258,10 @@ namespace X86ISA
typedef int RegContextVal;
typedef uint16_t RegIndex;
+
+ struct CoreSpecific {
+ int core_type;
+ };
};
#endif // __ARCH_X86_TYPES_HH__