diff options
Diffstat (limited to 'src/arch')
7 files changed, 498 insertions, 186 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 315705200..cb57bf9f0 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -595,172 +595,170 @@ } default: UD2(); } - } - 0x0E: decode LEGACY_DECODEVAL { - // no prefix - 0x0: decode OPCODE_OP_BOTTOM3 { - 0x0: pshufw_Pq_Qq_Ib(); - //0x1: group13_pshimw(); - 0x1: decode MODRM_REG { - 0x2: decode LEGACY_OP { - 0x0: psrlw_PRq_Ib(); - 0x1: psrlw_VRo_Ib(); + 0x0E: decode LEGACY_DECODEVAL { + // no prefix + 0x0: decode OPCODE_OP_BOTTOM3 { + 0x0: WarnUnimpl::pshufw_Pq_Qq_Ib(); + //0x1: group13_pshimw(); + 0x1: decode MODRM_REG { + 0x2: decode LEGACY_OP { + 0x0: PSRLW(PRq,Ib); + 0x1: PSRLW(VRo,Ib); + } + 0x4: decode LEGACY_OP { + 0x0: PSRAW(PRq,Ib); + 0x1: PSRAW(VRo,Ib); + } + 0x6: decode LEGACY_OP { + 0x0: PSLLW(PRq,Ib); + 0x1: PSLLW(VRo,Ib); + } + default: UD2(); } - 0x4: decode LEGACY_OP { - 0x0: psraw_PRq_Ib(); - 0x1: psraw_VRo_Ib(); + //0x2: group14_pshimd(); + 0x2: decode MODRM_REG { + 0x2: decode LEGACY_OP { + 0x0: PSRLD(PRq,Ib); + 0x1: PSRLD(VRo,Ib); + } + 0x4: decode LEGACY_OP { + 0x0: PSRAD(PRq,Ib); + 0x1: PSRAD(VRo,Ib); + } + 0x6: decode LEGACY_OP { + 0x0: PSLLD(PRq,Ib); + 0x1: PSLLD(VRo,Ib); + } + default: UD2(); } - 0x6: decode LEGACY_OP { - 0x0: psllw_PRq_Ib(); - 0x1: psllw_VRo_Ib(); + //0x3: group15_pshimq(); + 0x3: decode MODRM_REG { + 0x2: decode LEGACY_OP { + 0x0: PSRLQ(PRq,Ib); + 0x1: PSRLQ(VRo,Ib); + } + 0x3: decode LEGACY_OP { + 0x0: UD2(); + 0x1: WarnUnimpl::psrldq_VRo_Ib(); + } + 0x6: decode LEGACY_OP { + 0x0: PSLLQ(PRq,Ib); + 0x1: PSLLQ(VRo,Ib); + } + 0x7: decode LEGACY_OP { + 0x0: UD2(); + 0x1: WarnUnimpl::pslldq_VRo_Ib(); + } + default: Inst::UD2(); } - default: Inst::UD2(); + 0x4: Inst::PCMPEQB(Pq,Qq); + 0x5: Inst::PCMPEQW(Pq,Qq); + 0x6: Inst::PCMPEQD(Pq,Qq); + 0x7: WarnUnimpl::emms(); } - //0x2: group14_pshimd(); - 0x2: decode MODRM_REG { - 0x2: decode LEGACY_OP { - 0x0: psrld_PRq_Ib(); - 0x1: psrld_VRo_Ib(); - } - 0x4: decode LEGACY_OP { - 0x0: psrad_PRq_Ib(); - 0x1: psrad_VRo_Ib(); - } - 0x6: decode LEGACY_OP { - 0x0: pslld_PRq_Ib(); - 0x1: pslld_VRo_Ib(); - } - default: Inst::UD2(); + // repe (0xF3) + 0x4: decode OPCODE_OP_BOTTOM3 { + 0x0: WarnUnimpl::pshufhw_Vo_Wo_Ib(); + default: UD2(); } - //0x3: group15_pshimq(); - 0x3: decode MODRM_REG { - 0x2: decode LEGACY_OP { - 0x0: psrlq_PRq_Ib(); - 0x1: psrlq_VRo_Ib(); - } - 0x3: decode LEGACY_OP { - 0x0: Inst::UD2(); - 0x1: psrldq_VRo_Ib(); + // operand size (0x66) + 0x1: decode OPCODE_OP_BOTTOM3 { + 0x0: WarnUnimpl::pshufd_Vo_Wo_Ib(); + //0x1: group13_pshimw(); + 0x1: decode MODRM_REG { + 0x2: decode LEGACY_OP { + 0x0: PSRLW(PRq,Ib); + 0x1: PSRLW(VRo,Ib); + } + 0x4: decode LEGACY_OP { + 0x0: PSRAW(PRq,Ib); + 0x1: PSRAW(VRo,Ib); + } + 0x6: decode LEGACY_OP { + 0x0: PSLLW(PRq,Ib); + 0x1: PSLLW(VRo,Ib); + } + default: Inst::UD2(); } - 0x6: decode LEGACY_OP { - 0x0: psllq_PRq_Ib(); - 0x1: psllq_VRo_Ib(); + //0x2: group14_pshimd(); + 0x2: decode MODRM_REG { + 0x2: decode LEGACY_OP { + 0x0: PSRLD(PRq,Ib); + 0x1: PSRLD(VRo,Ib); + } + 0x4: decode LEGACY_OP { + 0x0: PSRAD(PRq,Ib); + 0x1: PSRAD(VRo,Ib); + } + 0x6: decode LEGACY_OP { + 0x0: PSLLD(PRq,Ib); + 0x1: PSLLD(VRo,Ib); + } + default: UD2(); } - 0x7: decode LEGACY_OP { - 0x0: Inst::UD2(); - 0x1: pslldq_VRo_Ib(); + //0x3: group15_pshimq(); + 0x3: decode MODRM_REG { + 0x2: decode LEGACY_OP { + 0x0: PSRLQ(PRq,Ib); + 0x1: PSRLQ(VRo,Ib); + } + 0x3: decode LEGACY_OP { + 0x0: UD2(); + 0x1: WarnUnimpl::psrldq_VRo_Ib(); + } + 0x6: decode LEGACY_OP { + 0x0: PSLLQ(PRq,Ib); + 0x1: PSLLQ(VRo,Ib); + } + 0x7: decode LEGACY_OP { + 0x0: UD2(); + 0x1: WarnUnimpl::pslldq_VRo_Ib(); + } + default: UD2(); } - default: Inst::UD2(); + 0x4: PCMPEQB(Vo,Wo); + 0x5: PCMPEQW(Vo,Wo); + 0x6: PCMPEQD(Vo,Wo); + default: UD2(); } - 0x4: Inst::PCMPEQB(Pq,Qq); - 0x5: Inst::PCMPEQW(Pq,Qq); - 0x6: Inst::PCMPEQD(Pq,Qq); - 0x7: emms(); - } - // repe (0xF3) - 0x4: decode OPCODE_OP_BOTTOM3 { - 0x0: pshufhw_Vo_Wo_Ib(); - default: Inst::UD2(); + // repne (0xF2) + 0x8: decode OPCODE_OP_BOTTOM3 { + 0x0: WarnUnimpl::pshuflw_Vo_Wo_Ib(); + default: UD2(); + } + default: UD2(); } - // operand size (0x66) - 0x1: decode OPCODE_OP_BOTTOM3 { - 0x0: pshufd_Vo_Wo_Ib(); - //0x1: group13_pshimw(); - 0x1: decode MODRM_REG { - 0x2: decode LEGACY_OP { - 0x0: psrlw_PRq_Ib(); - 0x1: psrlw_VRo_Ib(); - } - 0x4: decode LEGACY_OP { - 0x0: psraw_PRq_Ib(); - 0x1: psraw_VRo_Ib(); - } - 0x6: decode LEGACY_OP { - 0x0: psllw_PRq_Ib(); - 0x1: psllw_VRo_Ib(); - } - default: Inst::UD2(); + 0x0F: decode LEGACY_DECODEVAL { + // no prefix + 0x0: decode OPCODE_OP_BOTTOM3 { + 0x0: WarnUnimpl::vmread_Ed_or_Eq_Gd_or_Gq(); + 0x1: WarnUnimpl::vmwrite_Gd_or_Gq_Ed_or_Eq(); + 0x6: MOVD(Edp,Pdp); + 0x7: MOVQ(Qq,Pq); + default: UD2(); } - //0x2: group14_pshimd(); - 0x2: decode MODRM_REG { - 0x2: decode LEGACY_OP { - 0x0: psrld_PRq_Ib(); - 0x1: psrld_VRo_Ib(); - } - 0x4: decode LEGACY_OP { - 0x0: psrad_PRq_Ib(); - 0x1: psrad_VRo_Ib(); - } - 0x6: decode LEGACY_OP { - 0x0: pslld_PRq_Ib(); - 0x1: pslld_VRo_Ib(); - } - default: Inst::UD2(); + // repe (0xF3) + 0x4: decode OPCODE_OP_BOTTOM3 { + 0x6: MOVQ(Vq,Wq); + 0x7: WarnUnimpl::movdqu_Wo_Vo(); + default: UD2(); } - //0x3: group15_pshimq(); - 0x3: decode MODRM_REG { - 0x2: decode LEGACY_OP { - 0x0: psrlq_PRq_Ib(); - 0x1: psrlq_VRo_Ib(); - } - 0x3: decode LEGACY_OP { - 0x0: Inst::UD2(); - 0x1: psrldq_VRo_Ib(); - } - 0x6: decode LEGACY_OP { - 0x0: psllq_PRq_Ib(); - 0x1: psllq_VRo_Ib(); - } - 0x7: decode LEGACY_OP { - 0x0: Inst::UD2(); - 0x1: pslldq_VRo_Ib(); - } - default: Inst::UD2(); + // operand size (0x66) + 0x1: decode OPCODE_OP_BOTTOM3 { + 0x4: WarnUnimpl::haddpd_Vo_Wo(); + 0x5: WarnUnimpl::hsubpd_Vo_Wo(); + 0x6: WarnUnimpl::movd_Ed_Vd(); + 0x7: WarnUnimpl::movdqa_Wo_Vo(); + default: UD2(); } - 0x4: Inst::PCMPEQB(Vo,Wo); - 0x5: Inst::PCMPEQW(Vo,Wo); - 0x6: Inst::PCMPEQD(Vo,Wo); - default: Inst::UD2(); - } - // repne (0xF2) - 0x8: decode OPCODE_OP_BOTTOM3 { - 0x0: pshuflw_Vo_Wo_Ib(); - default: Inst::UD2(); - } - default: Inst::UD2(); - } - 0x0F: decode LEGACY_DECODEVAL { - // no prefix - 0x0: decode OPCODE_OP_BOTTOM3 { - 0x0: vmread_Ed_or_Eq_Gd_or_Gq(); - 0x1: vmwrite_Gd_or_Gq_Ed_or_Eq(); - 0x6: Inst::MOVD(Edp,Pdp); - 0x7: Inst::MOVQ(Qq,Pq); - default: Inst::UD2(); - } - // repe (0xF3) - 0x4: decode OPCODE_OP_BOTTOM3 { - 0x6: Inst::MOVQ(Vq,Wq); - 0x7: movdqu_Wo_Vo(); - default: Inst::UD2(); - } - // operand size (0x66) - 0x1: decode OPCODE_OP_BOTTOM3 { - 0x4: haddpd_Vo_Wo(); - 0x5: hsubpd_Vo_Wo(); - 0x6: movd_Ed_Vd(); - 0x7: movdqa_Wo_Vo(); - default: Inst::UD2(); - } - // repne (0xF2) - 0x8: decode OPCODE_OP_BOTTOM3 { - 0x4: haddps_Vo_Wo(); - 0x5: hsubps_Vo_Wo(); - default: Inst::UD2(); + // repne (0xF2) + 0x8: decode OPCODE_OP_BOTTOM3 { + 0x4: WarnUnimpl::haddps_Vo_Wo(); + 0x5: WarnUnimpl::hsubps_Vo_Wo(); + default: UD2(); + } + default: UD2(); } - default: Inst::UD2(); - } - format Inst { 0x10: decode OPCODE_OP_BOTTOM3 { 0x0: JO(Jz); 0x1: JNO(Jz); @@ -944,9 +942,9 @@ 0x1A: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { - 0x1: psrlw_Pq_Qq(); - 0x2: psrld_Pq_Qq(); - 0x3: psrlq_Pq_Qq(); + 0x1: Inst::PSRLW(Pq,Qq); + 0x2: Inst::PSRLD(Pq,Qq); + 0x3: Inst::PSRLQ(Pq,Qq); 0x4: Inst::PADDQ(Pq,Qq); 0x5: Inst::PMULLW(Pq,Qq); 0x7: pmovmskb_Gd_PRq(); @@ -960,9 +958,9 @@ // operand size (0x66) 0x1: decode OPCODE_OP_BOTTOM3 { 0x0: addsubpd_Vo_Wo(); - 0x1: psrlw_Vo_Wo(); - 0x2: psrld_Vo_Wo(); - 0x3: psrlq_Vo_Wo(); + 0x1: Inst::PSRLW(Vo,Wo); + 0x2: Inst::PSRLD(Vo,Wo); + 0x3: Inst::PSRLQ(Vo,Wo); 0x4: Inst::PADDQ(Vo,Wo); 0x5: Inst::PMULLW(Vo,Wo); 0x6: Inst::MOVQ(Wq,Vq); @@ -1007,8 +1005,8 @@ // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { 0x0: pavgb_Pq_Qq(); - 0x1: psraw_Pq_Qq(); - 0x2: psrad_Pq_Qq(); + 0x1: Inst::PSRAW(Pq,Qq); + 0x2: Inst::PSRAD(Pq,Qq); 0x3: pavgw_Pq_Qq(); 0x4: Inst::PMULHUW(Pq,Qq); 0x5: Inst::PMULHW(Pq,Qq); @@ -1023,8 +1021,8 @@ // operand size (0x66) 0x1: decode OPCODE_OP_BOTTOM3 { 0x0: pavgb_Vo_Wo(); - 0x1: psraw_Vo_Wo(); - 0x2: psrad_Vo_Wo(); + 0x1: Inst::PSRAW(Vo,Wo); + 0x2: Inst::PSRAD(Vo,Wo); 0x3: pavgw_Vo_Wo(); 0x4: Inst::PMULHUW(Vo,Wo); 0x5: Inst::PMULHW(Vo,Wo); @@ -1068,9 +1066,9 @@ 0x1E: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { - 0x1: psllw_Pq_Qq(); - 0x2: pslld_Pq_Qq(); - 0x3: psllq_Pq_Qq(); + 0x1: Inst::PSLLW(Pq,Qq); + 0x2: Inst::PSLLD(Pq,Qq); + 0x3: Inst::PSLLQ(Pq,Qq); 0x4: Inst::PMULUDQ(Pq,Qq); 0x5: pmaddwd_Pq_Qq(); 0x6: Inst::PSADBW(Pq,Qq); @@ -1079,9 +1077,9 @@ } // operand size (0x66) 0x1: decode OPCODE_OP_BOTTOM3 { - 0x1: psllw_Vo_Wo(); - 0x2: pslld_Vo_Wo(); - 0x3: psllq_Vo_Wo(); + 0x1: Inst::PSLLW(Vo,Wo); + 0x2: Inst::PSLLD(Vo,Wo); + 0x3: Inst::PSLLQ(Vo,Wo); 0x4: Inst::PMULUDQ(Vo,Wo); 0x5: pmaddwd_Vo_Wo(); 0x6: Inst::PSADBW(Vo,Wo); diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py index 18d6feb24..617033bc0 100644 --- a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py +++ b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py @@ -54,8 +54,73 @@ # Authors: Gabe Black microcode = ''' -# PSLLW -# PSLLD -# PSLLQ -# PSLLDQ +def macroop PSLLW_XMM_XMM { + msll xmmh, xmmh, xmmlm, size=2, ext=0 + msll xmml, xmml, xmmlm, size=2, ext=0 +}; + +def macroop PSLLW_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll xmml, xmml, ufp1, size=2, ext=0 + msll xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSLLW_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll xmml, xmml, ufp1, size=2, ext=0 + msll xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSLLW_XMM_I { + mslli xmml, xmml, imm, size=2, ext=0 + mslli xmmh, xmmh, imm, size=2, ext=0 +}; + +def macroop PSLLD_XMM_XMM { + msll xmmh, xmmh, xmmlm, size=4, ext=0 + msll xmml, xmml, xmmlm, size=4, ext=0 +}; + +def macroop PSLLD_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll xmml, xmml, ufp1, size=4, ext=0 + msll xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSLLD_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll xmml, xmml, ufp1, size=4, ext=0 + msll xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSLLD_XMM_I { + mslli xmml, xmml, imm, size=4, ext=0 + mslli xmmh, xmmh, imm, size=4, ext=0 +}; + +def macroop PSLLQ_XMM_XMM { + msll xmmh, xmmh, xmmlm, size=8, ext=0 + msll xmml, xmml, xmmlm, size=8, ext=0 +}; + +def macroop PSLLQ_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll xmml, xmml, ufp1, size=8, ext=0 + msll xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSLLQ_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll xmml, xmml, ufp1, size=8, ext=0 + msll xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSLLQ_XMM_I { + mslli xmml, xmml, imm, size=8, ext=0 + mslli xmmh, xmmh, imm, size=8, ext=0 +}; ''' +# PSLLDQ diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py index 63750e292..b88457a02 100644 --- a/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py +++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py @@ -54,6 +54,49 @@ # Authors: Gabe Black microcode = ''' -# PSRAW -# PSRAD +def macroop PSRAW_XMM_XMM { + msra xmmh, xmmh, xmmlm, size=2, ext=0 + msra xmml, xmml, xmmlm, size=2, ext=0 +}; + +def macroop PSRAW_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msra xmml, xmml, ufp1, size=2, ext=0 + msra xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRAW_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msra xmml, xmml, ufp1, size=2, ext=0 + msra xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRAW_XMM_I { + msrai xmml, xmml, imm, size=2, ext=0 + msrai xmmh, xmmh, imm, size=2, ext=0 +}; + +def macroop PSRAD_XMM_XMM { + msra xmmh, xmmh, xmmlm, size=4, ext=0 + msra xmml, xmml, xmmlm, size=4, ext=0 +}; + +def macroop PSRAD_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msra xmml, xmml, ufp1, size=4, ext=0 + msra xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRAD_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msra xmml, xmml, ufp1, size=4, ext=0 + msra xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRAD_XMM_I { + msrai xmml, xmml, imm, size=4, ext=0 + msrai xmmh, xmmh, imm, size=4, ext=0 +}; ''' diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py index fc6fb180b..c904eaf50 100644 --- a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py +++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py @@ -54,8 +54,73 @@ # Authors: Gabe Black microcode = ''' -# PSRLW -# PSRLD -# PSRLQ -# PSRLDQ +def macroop PSRLW_XMM_XMM { + msrl xmmh, xmmh, xmmlm, size=2, ext=0 + msrl xmml, xmml, xmmlm, size=2, ext=0 +}; + +def macroop PSRLW_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=2, ext=0 + msrl xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRLW_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=2, ext=0 + msrl xmmh, xmmh, ufp1, size=2, ext=0 +}; + +def macroop PSRLW_XMM_I { + msrli xmml, xmml, imm, size=2, ext=0 + msrli xmmh, xmmh, imm, size=2, ext=0 +}; + +def macroop PSRLD_XMM_XMM { + msrl xmmh, xmmh, xmmlm, size=4, ext=0 + msrl xmml, xmml, xmmlm, size=4, ext=0 +}; + +def macroop PSRLD_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=4, ext=0 + msrl xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRLD_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=4, ext=0 + msrl xmmh, xmmh, ufp1, size=4, ext=0 +}; + +def macroop PSRLD_XMM_I { + msrli xmml, xmml, imm, size=4, ext=0 + msrli xmmh, xmmh, imm, size=4, ext=0 +}; + +def macroop PSRLQ_XMM_XMM { + msrl xmmh, xmmh, xmmlm, size=8, ext=0 + msrl xmml, xmml, xmmlm, size=8, ext=0 +}; + +def macroop PSRLQ_XMM_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=8, ext=0 + msrl xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSRLQ_XMM_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl xmml, xmml, ufp1, size=8, ext=0 + msrl xmmh, xmmh, ufp1, size=8, ext=0 +}; + +def macroop PSRLQ_XMM_I { + msrli xmml, xmml, imm, size=8, ext=0 + msrli xmmh, xmmh, imm, size=8, ext=0 +}; ''' +# PSRLDQ diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py index 4687cab8d..011337ef7 100644 --- a/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py +++ b/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py @@ -54,7 +54,60 @@ # Authors: Gabe Black microcode = ''' -# PSLLW -# PSLLD -# PSLLQ +def macroop PSLLW_MMX_MMX { + msll mmx, mmx, mmxm, size=2, ext=0 +}; + +def macroop PSLLW_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll mmx, mmx, ufp1, size=2, ext=0 +}; + +def macroop PSLLW_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll mmx, mmx, ufp1, size=2, ext=0 +}; + +def macroop PSLLW_MMX_I { + mslli mmx, mmx, imm, size=2, ext=0 +}; + +def macroop PSLLD_MMX_MMX { + msll mmx, mmx, mmxm, size=4, ext=0 +}; + +def macroop PSLLD_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll mmx, mmx, ufp1, size=4, ext=0 +}; + +def macroop PSLLD_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll mmx, mmx, ufp1, size=4, ext=0 +}; + +def macroop PSLLD_MMX_I { + mslli mmx, mmx, imm, size=4, ext=0 +}; + +def macroop PSLLQ_MMX_MMX { + msll mmx, mmx, mmxm, size=8, ext=0 +}; + +def macroop PSLLQ_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msll mmx, mmx, ufp1, size=8, ext=0 +}; + +def macroop PSLLQ_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msll mmx, mmx, ufp1, size=8, ext=0 +}; + +def macroop PSLLQ_MMX_I { + mslli mmx, mmx, imm, size=8, ext=0 +}; ''' diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py index 63750e292..951b3ea9f 100644 --- a/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py +++ b/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py @@ -54,6 +54,41 @@ # Authors: Gabe Black microcode = ''' -# PSRAW -# PSRAD +def macroop PSRAW_MMX_MMX { + msra mmx, mmx, mmxm, size=2, ext=0 +}; + +def macroop PSRAW_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msra mmx, mmx, ufp1, size=2, ext=0 +}; + +def macroop PSRAW_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msra mmx, mmx, ufp1, size=2, ext=0 +}; + +def macroop PSRAW_MMX_I { + msrai mmx, mmx, imm, size=2, ext=0 +}; + +def macroop PSRAD_MMX_MMX { + msra mmx, mmx, mmxm, size=4, ext=0 +}; + +def macroop PSRAD_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msra mmx, mmx, ufp1, size=4, ext=0 +}; + +def macroop PSRAD_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msra mmx, mmx, ufp1, size=4, ext=0 +}; + +def macroop PSRAD_MMX_I { + msrai mmx, mmx, imm, size=4, ext=0 +}; ''' diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py index 1f870dc32..dc6182de7 100644 --- a/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py +++ b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py @@ -54,7 +54,60 @@ # Authors: Gabe Black microcode = ''' -# PSRLW -# PSRLD -# PSRLQ +def macroop PSRLW_MMX_MMX { + msrl mmx, mmx, mmxm, size=2, ext=0 +}; + +def macroop PSRLW_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl mmx, mmx, ufp1, size=2, ext=0 +}; + +def macroop PSRLW_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl mmx, mmx, ufp1, size=2, ext=0 +}; + +def macroop PSRLW_MMX_I { + msrli mmx, mmx, imm, size=2, ext=0 +}; + +def macroop PSRLD_MMX_MMX { + msrl mmx, mmx, mmxm, size=4, ext=0 +}; + +def macroop PSRLD_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl mmx, mmx, ufp1, size=4, ext=0 +}; + +def macroop PSRLD_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl mmx, mmx, ufp1, size=4, ext=0 +}; + +def macroop PSRLD_MMX_I { + msrli mmx, mmx, imm, size=4, ext=0 +}; + +def macroop PSRLQ_MMX_MMX { + msrl mmx, mmx, mmxm, size=8, ext=0 +}; + +def macroop PSRLQ_MMX_M { + ldfp ufp1, seg, sib, disp, dataSize=8 + msrl mmx, mmx, ufp1, size=8, ext=0 +}; + +def macroop PSRLQ_MMX_P { + rdip t7 + ldfp ufp1, seg, riprel, disp, dataSize=8 + msrl mmx, mmx, ufp1, size=8, ext=0 +}; + +def macroop PSRLQ_MMX_I { + msrli mmx, mmx, imm, size=8, ext=0 +}; ''' |