diff options
Diffstat (limited to 'src/arch')
50 files changed, 467 insertions, 467 deletions
diff --git a/src/arch/alpha/arguments.cc b/src/arch/alpha/arguments.cc index f19ed7ff7..9f9002003 100644 --- a/src/arch/alpha/arguments.cc +++ b/src/arch/alpha/arguments.cc @@ -30,7 +30,7 @@ #include "arch/alpha/arguments.hh" #include "arch/alpha/vtophys.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" using namespace AlphaISA; @@ -56,14 +56,14 @@ AlphaArguments::getArg(bool fp) { if (number < 6) { if (fp) - return xc->readFloatRegBits(16 + number); + return tc->readFloatRegBits(16 + number); else - return xc->readIntReg(16 + number); + return tc->readIntReg(16 + number); } else { - Addr sp = xc->readIntReg(30); - VirtualPort *vp = xc->getVirtPort(xc); + Addr sp = tc->readIntReg(30); + VirtualPort *vp = tc->getVirtPort(tc); uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t)); - xc->delVirtPort(vp); + tc->delVirtPort(vp); return arg; } } diff --git a/src/arch/alpha/arguments.hh b/src/arch/alpha/arguments.hh index 11a67f3d4..d977d48d6 100644 --- a/src/arch/alpha/arguments.hh +++ b/src/arch/alpha/arguments.hh @@ -37,14 +37,14 @@ #include "base/refcnt.hh" #include "sim/host.hh" -class ExecContext; +class ThreadContext; namespace AlphaISA { class AlphaArguments { protected: - ExecContext *xc; + ThreadContext *tc; int number; uint64_t getArg(bool fp = false); @@ -65,17 +65,17 @@ class AlphaArguments RefCountingPtr<Data> data; public: - AlphaArguments(ExecContext *ctx, int n = 0) - : xc(ctx), number(n), data(NULL) + AlphaArguments(ThreadContext *ctx, int n = 0) + : tc(ctx), number(n), data(NULL) { assert(number >= 0); data = new Data;} AlphaArguments(const AlphaArguments &args) - : xc(args.xc), number(args.number), data(args.data) {} + : tc(args.tc), number(args.number), data(args.data) {} ~AlphaArguments() {} - ExecContext *getExecContext() const { return xc; } + ThreadContext *getThreadContext() const { return tc; } const AlphaArguments &operator=(const AlphaArguments &args) { - xc = args.xc; + tc = args.tc; number = args.number; data = args.data; return *this; @@ -120,7 +120,7 @@ class AlphaArguments } AlphaArguments operator[](int index) { - return AlphaArguments(xc, index); + return AlphaArguments(tc, index); } template <class T> @@ -133,13 +133,13 @@ class AlphaArguments template <class T> operator T *() { T *buf = (T *)data->alloc(sizeof(T)); - CopyData(xc, buf, getArg(), sizeof(T)); + CopyData(tc, buf, getArg(), sizeof(T)); return buf; } operator char *() { char *buf = data->alloc(2048); - CopyStringOut(xc, buf, getArg(), 2048); + CopyStringOut(tc, buf, getArg(), 2048); return buf; } }; diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 5be185002..50ce6b78a 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -38,7 +38,7 @@ #include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/cpu_exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/kernel_stats.hh" #include "sim/debug.hh" #include "sim/sim_events.hh" @@ -52,15 +52,15 @@ using namespace EV5; // Machine dependent functions // void -AlphaISA::initCPU(ExecContext *xc, int cpuId) +AlphaISA::initCPU(ThreadContext *tc, int cpuId) { - initIPRs(xc, cpuId); + initIPRs(tc, cpuId); - xc->setIntReg(16, cpuId); - xc->setIntReg(0, cpuId); + tc->setIntReg(16, cpuId); + tc->setIntReg(0, cpuId); - xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); - xc->setNextPC(xc->readPC() + sizeof(MachInst)); + tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); + tc->setNextPC(tc->readPC() + sizeof(MachInst)); } //////////////////////////////////////////////////////////////////////// @@ -68,15 +68,15 @@ AlphaISA::initCPU(ExecContext *xc, int cpuId) // // void -AlphaISA::initIPRs(ExecContext *xc, int cpuId) +AlphaISA::initIPRs(ThreadContext *tc, int cpuId) { for (int i = 0; i < NumInternalProcRegs; ++i) { - xc->setMiscReg(i, 0); + tc->setMiscReg(i, 0); } - xc->setMiscReg(IPR_PAL_BASE, PalBase); - xc->setMiscReg(IPR_MCSR, 0x6); - xc->setMiscReg(IPR_PALtemp16, cpuId); + tc->setMiscReg(IPR_PAL_BASE, PalBase); + tc->setMiscReg(IPR_MCSR, 0x6); + tc->setMiscReg(IPR_PALtemp16, cpuId); } @@ -171,7 +171,7 @@ AlphaISA::MiscRegFile::getDataAsid() } AlphaISA::MiscReg -AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) +AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) { uint64_t retval = 0; // return value, default 0 @@ -225,7 +225,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) case AlphaISA::IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); + retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); break; case AlphaISA::IPR_VA: @@ -242,7 +242,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) case AlphaISA::IPR_DTB_PTE: { - AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating()); + AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; @@ -282,11 +282,11 @@ int break_ipl = -1; #endif Fault -AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) +AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) { uint64_t old; - if (xc->misspeculating()) + if (tc->misspeculating()) return NoFault; switch (idx) { @@ -339,8 +339,8 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; - if (xc->getKernelStats()) - xc->getKernelStats()->context(old, val, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->context(old, val, tc); break; case AlphaISA::IPR_DTB_PTE: @@ -367,17 +367,17 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; - if (xc->getKernelStats()) - xc->getKernelStats()->swpipl(ipr[idx]); + if (tc->getKernelStats()) + tc->getKernelStats()->swpipl(ipr[idx]); break; case AlphaISA::IPR_DTB_CM: if (val & 0x18) { - if (xc->getKernelStats()) - xc->getKernelStats()->mode(Kernel::user, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->mode(Kernel::user, tc); } else { - if (xc->getKernelStats()) - xc->getKernelStats()->mode(Kernel::kernel, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->mode(Kernel::kernel, tc); } case AlphaISA::IPR_ICM: @@ -452,21 +452,21 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // really a control write ipr[idx] = 0; - xc->getDTBPtr()->flushAll(); + tc->getDTBPtr()->flushAll(); break; case AlphaISA::IPR_DTB_IAP: // really a control write ipr[idx] = 0; - xc->getDTBPtr()->flushProcesses(); + tc->getDTBPtr()->flushProcesses(); break; case AlphaISA::IPR_DTB_IS: // really a control write ipr[idx] = val; - xc->getDTBPtr()->flushAddr(val, + tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); break; @@ -490,7 +490,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB - xc->getDTBPtr()->insert(val, pte); + tc->getDTBPtr()->insert(val, pte); } break; @@ -514,7 +514,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); + tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); } break; @@ -522,21 +522,21 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // really a control write ipr[idx] = 0; - xc->getITBPtr()->flushAll(); + tc->getITBPtr()->flushAll(); break; case AlphaISA::IPR_ITB_IAP: // really a control write ipr[idx] = 0; - xc->getITBPtr()->flushProcesses(); + tc->getITBPtr()->flushProcesses(); break; case AlphaISA::IPR_ITB_IS: // really a control write ipr[idx] = val; - xc->getITBPtr()->flushAddr(val, + tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); break; @@ -550,7 +550,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) } void -AlphaISA::copyIprs(ExecContext *src, ExecContext *dest) +AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) { for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { dest->setMiscReg(i, src->readMiscReg(i)); @@ -565,7 +565,7 @@ bool CPUExecContext::simPalCheck(int palFunc) { if (kernelStats) - kernelStats->callpal(palFunc, proxy); + kernelStats->callpal(palFunc, tc); switch (palFunc) { case PAL::halt: diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 88084bf86..8493223ff 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -30,7 +30,7 @@ */ #include "arch/alpha/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" #if FULL_SYSTEM @@ -110,67 +110,67 @@ FaultStat IntegerOverflowFault::_count; #if FULL_SYSTEM -void AlphaFault::invoke(ExecContext * xc) +void AlphaFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); countStat()++; // exception restart address - if (setRestartAddress() || !xc->inPalMode()) - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC()); + if (setRestartAddress() || !tc->inPalMode()) + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC()); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, - xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, + tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); } - xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); - xc->setNextPC(xc->readPC() + sizeof(MachInst)); + tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); + tc->setNextPC(tc->readPC() + sizeof(MachInst)); } -void ArithmeticFault::invoke(ExecContext * xc) +void ArithmeticFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); panic("Arithmetic traps are unimplemented!"); } -void DtbFault::invoke(ExecContext * xc) +void DtbFault::invoke(ThreadContext * tc) { // Set fault address and flags. Even though we're modeling an // EV5, we use the EV6 technique of not latching fault registers // on VPTE loads (instead of locking the registers until IPR_VA is // read, like the EV5). The EV6 approach is cleaner and seems to // work with EV5 PAL code, but not the other way around. - if (!xc->misspeculating() + if (!tc->misspeculating() && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { // set VA register with faulting address - xc->setMiscReg(AlphaISA::IPR_VA, vaddr); + tc->setMiscReg(AlphaISA::IPR_VA, vaddr); // set MM_STAT register flags - xc->setMiscReg(AlphaISA::IPR_MM_STAT, - (((EV5::Opcode(xc->getInst()) & 0x3f) << 11) - | ((EV5::Ra(xc->getInst()) & 0x1f) << 6) + tc->setMiscReg(AlphaISA::IPR_MM_STAT, + (((EV5::Opcode(tc->getInst()) & 0x3f) << 11) + | ((EV5::Ra(tc->getInst()) & 0x1f) << 6) | (flags & 0x3f))); // set VA_FORM register with faulting formatted address - xc->setMiscReg(AlphaISA::IPR_VA_FORM, - xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); + tc->setMiscReg(AlphaISA::IPR_VA_FORM, + tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); } - AlphaFault::invoke(xc); + AlphaFault::invoke(tc); } -void ItbFault::invoke(ExecContext * xc) +void ItbFault::invoke(ThreadContext * tc) { - if (!xc->misspeculating()) { - xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); - xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, - xc->readMiscReg(AlphaISA::IPR_IVPTBR) | + if (!tc->misspeculating()) { + tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); + tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, + tc->readMiscReg(AlphaISA::IPR_IVPTBR) | (AlphaISA::VAddr(pc).vpn() << 3)); } - AlphaFault::invoke(xc); + AlphaFault::invoke(tc); } #endif diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh index 0d60367f7..f952cf9d6 100644 --- a/src/arch/alpha/faults.hh +++ b/src/arch/alpha/faults.hh @@ -49,7 +49,7 @@ class AlphaFault : public FaultBase virtual bool setRestartAddress() {return true;} public: #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif virtual FaultVect vect() = 0; virtual FaultStat & countStat() = 0; @@ -116,7 +116,7 @@ class ArithmeticFault : public AlphaFault FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; @@ -150,7 +150,7 @@ class DtbFault : public AlphaFault FaultVect vect() = 0; FaultStat & countStat() = 0; #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; @@ -251,7 +251,7 @@ class ItbFault : public AlphaFault FaultVect vect() = 0; FaultStat & countStat() = 0; #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; diff --git a/src/arch/alpha/freebsd/system.cc b/src/arch/alpha/freebsd/system.cc index 2781fed3d..91f8b5af1 100644 --- a/src/arch/alpha/freebsd/system.cc +++ b/src/arch/alpha/freebsd/system.cc @@ -38,7 +38,7 @@ #include "arch/alpha/system.hh" #include "arch/alpha/freebsd/system.hh" #include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/physical.hh" #include "mem/port.hh" #include "arch/isa_traits.hh" @@ -72,13 +72,13 @@ FreebsdAlphaSystem::~FreebsdAlphaSystem() void -FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc) +FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc) { Addr ppc_vaddr = 0; Addr timer_vaddr = 0; - ppc_vaddr = (Addr)xc->readIntReg(ArgumentReg1); - timer_vaddr = (Addr)xc->readIntReg(ArgumentReg2); + ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1); + timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2); virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency); virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY); @@ -86,10 +86,10 @@ FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc) void -FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc) +FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc) { - SkipFuncEvent::process(xc); - ((FreebsdAlphaSystem *)xc->getSystemPtr())->doCalibrateClocks(xc); + SkipFuncEvent::process(tc); + ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc); } diff --git a/src/arch/alpha/freebsd/system.hh b/src/arch/alpha/freebsd/system.hh index 46a5e665c..e0d874e8f 100644 --- a/src/arch/alpha/freebsd/system.hh +++ b/src/arch/alpha/freebsd/system.hh @@ -42,7 +42,7 @@ class FreebsdAlphaSystem : public AlphaSystem SkipCalibrateClocksEvent(PCEventQueue *q, const std::string &desc, Addr addr) : SkipFuncEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; SkipFuncEvent *skipDelayEvent; @@ -51,7 +51,7 @@ class FreebsdAlphaSystem : public AlphaSystem public: FreebsdAlphaSystem(Params *p); ~FreebsdAlphaSystem(); - void doCalibrateClocks(ExecContext *xc); + void doCalibrateClocks(ThreadContext *tc); }; diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa index aa7abf289..7438e7e18 100644 --- a/src/arch/alpha/isa/branch.isa +++ b/src/arch/alpha/isa/branch.isa @@ -106,7 +106,7 @@ output header {{ { } - Addr branchTarget(ExecContext *xc) const; + Addr branchTarget(ThreadContext *tc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -121,10 +121,10 @@ output decoder {{ } Addr - Jump::branchTarget(ExecContext *xc) const + Jump::branchTarget(ThreadContext *tc) const { - Addr NPC = xc->readPC() + 4; - uint64_t Rb = xc->readIntReg(_srcRegIdx[0]); + Addr NPC = tc->readPC() + 4; + uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); return (Rb & ~3) | (NPC & 1); } diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 6e19f2343..fab2ca2e1 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -765,56 +765,56 @@ decode OPCODE default Unknown::unknown() { // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { 0x00: arm({{ - AlphaPseudo::arm(xc->xcBase()); + AlphaPseudo::arm(xc->tcBase()); }}, IsNonSpeculative); 0x01: quiesce({{ - AlphaPseudo::quiesce(xc->xcBase()); + AlphaPseudo::quiesce(xc->tcBase()); }}, IsNonSpeculative, IsQuiesce); 0x02: quiesceNs({{ - AlphaPseudo::quiesceNs(xc->xcBase(), R16); + AlphaPseudo::quiesceNs(xc->tcBase(), R16); }}, IsNonSpeculative, IsQuiesce); 0x03: quiesceCycles({{ - AlphaPseudo::quiesceCycles(xc->xcBase(), R16); + AlphaPseudo::quiesceCycles(xc->tcBase(), R16); }}, IsNonSpeculative, IsQuiesce); 0x04: quiesceTime({{ - R0 = AlphaPseudo::quiesceTime(xc->xcBase()); + R0 = AlphaPseudo::quiesceTime(xc->tcBase()); }}, IsNonSpeculative); 0x10: ivlb({{ - AlphaPseudo::ivlb(xc->xcBase()); + AlphaPseudo::ivlb(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x11: ivle({{ - AlphaPseudo::ivle(xc->xcBase()); + AlphaPseudo::ivle(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x20: m5exit_old({{ - AlphaPseudo::m5exit_old(xc->xcBase()); + AlphaPseudo::m5exit_old(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x21: m5exit({{ - AlphaPseudo::m5exit(xc->xcBase(), R16); + AlphaPseudo::m5exit(xc->tcBase(), R16); }}, No_OpClass, IsNonSpeculative); - 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); + 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }}); 0x40: resetstats({{ - AlphaPseudo::resetstats(xc->xcBase(), R16, R17); + AlphaPseudo::resetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x41: dumpstats({{ - AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); + AlphaPseudo::dumpstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x42: dumpresetstats({{ - AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); + AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x43: m5checkpoint({{ - AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); + AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x50: m5readfile({{ - R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); + R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18); }}, IsNonSpeculative); 0x51: m5break({{ - AlphaPseudo::debugbreak(xc->xcBase()); + AlphaPseudo::debugbreak(xc->tcBase()); }}, IsNonSpeculative); 0x52: m5switchcpu({{ - AlphaPseudo::switchcpu(xc->xcBase()); + AlphaPseudo::switchcpu(xc->tcBase()); }}, IsNonSpeculative); 0x53: m5addsymbol({{ - AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); + AlphaPseudo::addsymbol(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x54: m5panic({{ panic("M5 panic instruction called at pc=%#x.", xc->readPC()); diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 91ece0935..1270bf8d8 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -56,7 +56,7 @@ output decoder {{ #include "base/fenv.hh" #include "base/loader/symtab.hh" #include "config/ss_compatible_fp.hh" -#include "cpu/exec_context.hh" // for Jump::branchTarget() +#include "cpu/thread_context.hh" // for Jump::branchTarget() #include <math.h> diff --git a/src/arch/alpha/linux/process.cc b/src/arch/alpha/linux/process.cc index abd17c224..997c78ac9 100644 --- a/src/arch/alpha/linux/process.cc +++ b/src/arch/alpha/linux/process.cc @@ -34,7 +34,7 @@ #include "arch/alpha/isa_traits.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/linux.hh" #include "sim/process.hh" @@ -48,9 +48,9 @@ using namespace AlphaISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -58,7 +58,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "alpha"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } @@ -67,18 +67,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, /// different in practice from those used by Tru64 processes. static SyscallReturn osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 45: { // GSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR *fpcr = 0; - fpcr.copyOut(xc->getMemPort()); + fpcr.copyOut(tc->getMemPort()); return 0; } @@ -94,17 +94,17 @@ osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target osf_setsysinfo() handler. static SyscallReturn osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 14: { // SSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR - fpcr.copyIn(xc->getMemPort()); + fpcr.copyIn(tc->getMemPort()); DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): " " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); return 0; diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index f267e9d42..e6c6f42e9 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -46,7 +46,7 @@ #include "arch/alpha/linux/threadinfo.hh" #include "arch/alpha/system.hh" #include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "dev/platform.hh" #include "kern/linux/printk.hh" @@ -175,30 +175,30 @@ LinuxAlphaSystem::~LinuxAlphaSystem() void -LinuxAlphaSystem::setDelayLoop(ExecContext *xc) +LinuxAlphaSystem::setDelayLoop(ThreadContext *tc) { Addr addr = 0; if (kernelSymtab->findAddress("loops_per_jiffy", addr)) { - Tick cpuFreq = xc->getCpuPtr()->frequency(); + Tick cpuFreq = tc->getCpuPtr()->frequency(); Tick intrFreq = platform->intrFrequency(); - xc->getVirtPort(xc)->write(addr, + tc->getVirtPort(tc)->write(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988)); } } void -LinuxAlphaSystem::SkipDelayLoopEvent::process(ExecContext *xc) +LinuxAlphaSystem::SkipDelayLoopEvent::process(ThreadContext *tc) { - SkipFuncEvent::process(xc); + SkipFuncEvent::process(tc); // calculate and set loops_per_jiffy - ((LinuxAlphaSystem *)xc->getSystemPtr())->setDelayLoop(xc); + ((LinuxAlphaSystem *)tc->getSystemPtr())->setDelayLoop(tc); } void -LinuxAlphaSystem::PrintThreadInfo::process(ExecContext *xc) +LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc) { - Linux::ThreadInfo ti(xc); + Linux::ThreadInfo ti(tc); DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n", ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart()); diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh index 46bf6ea91..c03586ac5 100644 --- a/src/arch/alpha/linux/system.hh +++ b/src/arch/alpha/linux/system.hh @@ -33,7 +33,7 @@ #ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__ #define __ARCH_ALPHA_LINUX_SYSTEM_HH__ -class ExecContext; +class ThreadContext; class BreakPCEvent; class IdleStartEvent; @@ -57,7 +57,7 @@ class LinuxAlphaSystem : public AlphaSystem public: SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr) : SkipFuncEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class PrintThreadInfo : public PCEvent @@ -65,7 +65,7 @@ class LinuxAlphaSystem : public AlphaSystem public: PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; @@ -143,7 +143,7 @@ class LinuxAlphaSystem : public AlphaSystem LinuxAlphaSystem(Params *p); ~LinuxAlphaSystem(); - void setDelayLoop(ExecContext *xc); + void setDelayLoop(ThreadContext *tc); }; #endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__ diff --git a/src/arch/alpha/linux/threadinfo.hh b/src/arch/alpha/linux/threadinfo.hh index 74444f427..caeb69f15 100644 --- a/src/arch/alpha/linux/threadinfo.hh +++ b/src/arch/alpha/linux/threadinfo.hh @@ -33,7 +33,7 @@ #define __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__ #include "arch/alpha/linux/thread_info.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/sched.hh" #include "sim/vptr.hh" @@ -42,10 +42,10 @@ namespace Linux { class ThreadInfo { private: - ExecContext *xc; + ThreadContext *tc; public: - ThreadInfo(ExecContext *exec) : xc(exec) {} + ThreadInfo(ThreadContext *_tc) : tc(_tc) {} ~ThreadInfo() {} inline VPtr<thread_info> @@ -57,15 +57,15 @@ class ThreadInfo * thread_info struct. So we can get the address by masking off * the lower 14 bits. */ - current = xc->readIntReg(TheISA::StackPointerReg) & ~0x3fff; - return VPtr<thread_info>(xc, current); + current = tc->readIntReg(TheISA::StackPointerReg) & ~0x3fff; + return VPtr<thread_info>(tc, current); } inline VPtr<task_struct> curTaskInfo() { Addr task = curThreadInfo()->task; - return VPtr<task_struct>(xc, task); + return VPtr<task_struct>(tc, task); } std::string diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 490e04972..4c0c68761 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -35,7 +35,7 @@ #include "arch/alpha/tru64/process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/builder.hh" #include "sim/system.hh" @@ -107,7 +107,7 @@ AlphaLiveProcess::startup() { argsInit(MachineBytes, VMPageSize); - execContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer()); + threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer()); } diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 2652144b6..ed410fddb 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -36,7 +36,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; namespace AlphaISA { @@ -90,7 +90,7 @@ namespace AlphaISA MiscReg readReg(int misc_reg); MiscReg readRegWithEffect(int misc_reg, Fault &fault, - ExecContext *xc); + ThreadContext *tc); //These functions should be removed once the simplescalar cpu model //has been replaced. @@ -100,7 +100,7 @@ namespace AlphaISA Fault setReg(int misc_reg, const MiscReg &val); Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc); + ThreadContext *tc); #if FULL_SYSTEM protected: @@ -109,9 +109,9 @@ namespace AlphaISA InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs private: - InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc); + InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc); - Fault setIpr(int idx, InternalProcReg val, ExecContext *xc); + Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc); #endif friend class RegFile; }; @@ -182,10 +182,10 @@ namespace AlphaISA } MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ExecContext *xc) + Fault &fault, ThreadContext *tc) { fault = NoFault; - return miscRegFile.readRegWithEffect(miscReg, fault, xc); + return miscRegFile.readRegWithEffect(miscReg, fault, tc); } Fault setMiscReg(int miscReg, const MiscReg &val) @@ -194,9 +194,9 @@ namespace AlphaISA } Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc) + ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, xc); + return miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg) @@ -268,12 +268,12 @@ namespace AlphaISA } }; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ExecContext *src, ExecContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); #if FULL_SYSTEM - void copyIprs(ExecContext *src, ExecContext *dest); + void copyIprs(ThreadContext *src, ThreadContext *dest); #endif } // namespace AlphaISA diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc index 792b63e2f..3519fd940 100644 --- a/src/arch/alpha/stacktrace.cc +++ b/src/arch/alpha/stacktrace.cc @@ -36,36 +36,36 @@ #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/system.hh" using namespace std; using namespace AlphaISA; -ProcessInfo::ProcessInfo(ExecContext *_xc) - : xc(_xc) +ProcessInfo::ProcessInfo(ThreadContext *_tc) + : tc(_tc) { Addr addr = 0; - if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) panic("thread info not compiled into kernel\n"); - thread_info_size = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + thread_info_size = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) panic("thread info not compiled into kernel\n"); - task_struct_size = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + task_struct_size = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) panic("thread info not compiled into kernel\n"); - task_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + task_off = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) panic("thread info not compiled into kernel\n"); - pid_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + pid_off = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) panic("thread info not compiled into kernel\n"); - name_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + name_off = gtoh(tc->getVirtPort()->read<int32_t>(addr)); } Addr @@ -75,7 +75,7 @@ ProcessInfo::task(Addr ksp) const if (base == ULL(0xfffffc0000000000)) return 0; - return gtoh(xc->getVirtPort()->read<Addr>(base + task_off)); + return gtoh(tc->getVirtPort()->read<Addr>(base + task_off)); } int @@ -85,7 +85,7 @@ ProcessInfo::pid(Addr ksp) const if (!task) return -1; - return gtoh(xc->getVirtPort()->read<uint16_t>(task + pid_off)); + return gtoh(tc->getVirtPort()->read<uint16_t>(task + pid_off)); } string @@ -96,7 +96,7 @@ ProcessInfo::name(Addr ksp) const return "console"; char comm[256]; - CopyStringOut(xc, comm, task + name_off, sizeof(comm)); + CopyStringOut(tc, comm, task + name_off, sizeof(comm)); if (!comm[0]) return "startup"; @@ -104,14 +104,14 @@ ProcessInfo::name(Addr ksp) const } StackTrace::StackTrace() - : xc(0), stack(64) + : tc(0), stack(64) { } -StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst) - : xc(0), stack(64) +StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) + : tc(0), stack(64) { - trace(_xc, inst); + trace(_tc, inst); } StackTrace::~StackTrace() @@ -119,15 +119,15 @@ StackTrace::~StackTrace() } void -StackTrace::trace(ExecContext *_xc, bool is_call) +StackTrace::trace(ThreadContext *_tc, bool is_call) { - xc = _xc; + tc = _tc; - bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; - Addr pc = xc->readNextPC(); - bool kernel = xc->getSystemPtr()->kernelStart <= pc && - pc <= xc->getSystemPtr()->kernelEnd; + Addr pc = tc->readNextPC(); + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; if (usermode) { stack.push_back(user); @@ -139,8 +139,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call) return; } - SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab; - Addr ksp = xc->readIntReg(TheISA::StackPointerReg); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + Addr ksp = tc->readIntReg(TheISA::StackPointerReg); Addr bottom = ksp & ~0x3fff; Addr addr; @@ -149,7 +149,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call) panic("could not find address %#x", pc); stack.push_back(addr); - pc = xc->readPC(); + pc = tc->readPC(); } Addr ra; @@ -181,8 +181,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call) return; } - bool kernel = xc->getSystemPtr()->kernelStart <= pc && - pc <= xc->getSystemPtr()->kernelEnd; + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; if (!kernel) return; @@ -196,22 +196,22 @@ StackTrace::trace(ExecContext *_xc, bool is_call) bool StackTrace::isEntry(Addr addr) { - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) return true; return false; @@ -296,7 +296,7 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { MachInst inst; - CopyOut(xc, (uint8_t *)&inst, pc, sizeof(MachInst)); + CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); int reg, disp; if (decodeStack(inst, disp)) { @@ -307,7 +307,7 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, size += disp; } else if (decodeSave(inst, reg, disp)) { if (!ra && reg == ReturnAddressReg) { - CopyOut(xc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); + CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); if (!ra) { // panic("no return address value pc=%#x\n", pc); return false; @@ -323,8 +323,8 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, void StackTrace::dump() { - StringWrap name(xc->getCpuPtr()->name()); - SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab; + StringWrap name(tc->getCpuPtr()->name()); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; DPRINTFN("------ Stack ------\n"); diff --git a/src/arch/alpha/stacktrace.hh b/src/arch/alpha/stacktrace.hh index dd86a1553..d12aee211 100644 --- a/src/arch/alpha/stacktrace.hh +++ b/src/arch/alpha/stacktrace.hh @@ -34,13 +34,13 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" -class ExecContext; +class ThreadContext; class StackTrace; class ProcessInfo { private: - ExecContext *xc; + ThreadContext *tc; int thread_info_size; int task_struct_size; @@ -49,7 +49,7 @@ class ProcessInfo int name_off; public: - ProcessInfo(ExecContext *_xc); + ProcessInfo(ThreadContext *_tc); Addr task(Addr ksp) const; int pid(Addr ksp) const; @@ -61,7 +61,7 @@ class StackTrace protected: typedef TheISA::MachInst MachInst; private: - ExecContext *xc; + ThreadContext *tc; std::vector<Addr> stack; private: @@ -70,21 +70,21 @@ class StackTrace bool decodeSave(MachInst inst, int ®, int &disp); bool decodeStack(MachInst inst, int &disp); - void trace(ExecContext *xc, bool is_call); + void trace(ThreadContext *tc, bool is_call); public: StackTrace(); - StackTrace(ExecContext *xc, StaticInstPtr inst); + StackTrace(ThreadContext *tc, StaticInstPtr inst); ~StackTrace(); void clear() { - xc = 0; + tc = 0; stack.clear(); } - bool valid() const { return xc != NULL; } - bool trace(ExecContext *xc, StaticInstPtr inst); + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); public: const std::vector<Addr> &getstack() const { return stack; } @@ -106,7 +106,7 @@ class StackTrace }; inline bool -StackTrace::trace(ExecContext *xc, StaticInstPtr inst) +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) { if (!inst->isCall() && !inst->isReturn()) return false; @@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst) if (valid()) clear(); - trace(xc, !inst->isReturn()); + trace(tc, !inst->isReturn()); return true; } diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 0bcca1887..c6684274b 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -38,7 +38,7 @@ #include "base/str.hh" #include "base/trace.hh" #include "config/alpha_tlaser.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/builder.hh" using namespace std; @@ -286,7 +286,7 @@ AlphaITB::regStats() Fault -AlphaITB::translate(RequestPtr &req, ExecContext *xc) const +AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const { if (AlphaISA::PcPAL(req->getVaddr())) { // strip off PAL PC marker (lsb is 1) @@ -308,13 +308,13 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER - if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && + if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && VAddrSpaceEV5(req->getVaddr()) == 2) { #else if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif // only valid in kernel mode - if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) != + if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) != AlphaISA::mode_kernel) { acv++; return new ItbAcvFault(req->getVaddr()); @@ -332,7 +332,7 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const } else { // not a physical address: need to look up pte - int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); + int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), asn); @@ -347,7 +347,7 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const // check permissions for this access if (!(pte->xre & - (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) { + (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) { // instruction access fault acv++; return new ItbAcvFault(req->getVaddr()); @@ -443,12 +443,12 @@ AlphaDTB::regStats() } Fault -AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const +AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const { - Addr pc = xc->readPC(); + Addr pc = tc->readPC(); AlphaISA::mode_type mode = - (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)); + (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)); /** @@ -464,7 +464,7 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const if (pc & 0x1) { mode = (req->getFlags() & ALTMODE) ? (AlphaISA::mode_type)ALT_MODE_AM( - xc->readMiscReg(AlphaISA::IPR_ALT_MODE)) + tc->readMiscReg(AlphaISA::IPR_ALT_MODE)) : AlphaISA::mode_kernel; } @@ -482,14 +482,14 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const // Check for "superpage" mapping #if ALPHA_TLASER - if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && + if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && VAddrSpaceEV5(req->getVaddr()) == 2) { #else if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif // only valid in kernel mode - if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) != + if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) != AlphaISA::mode_kernel) { if (write) { write_acv++; } else { read_acv++; } uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | @@ -513,7 +513,7 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const else read_accesses++; - int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); + int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); // not a physical address: need to look up pte AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 81719cc48..07d01fa5c 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -41,7 +41,7 @@ #include "mem/request.hh" #include "sim/sim_object.hh" -class ExecContext; +class ThreadContext; class AlphaTLB : public SimObject { @@ -95,7 +95,7 @@ class AlphaITB : public AlphaTLB AlphaITB(const std::string &name, int size); virtual void regStats(); - Fault translate(RequestPtr &req, ExecContext *xc) const; + Fault translate(RequestPtr &req, ThreadContext *tc) const; }; class AlphaDTB : public AlphaTLB @@ -118,7 +118,7 @@ class AlphaDTB : public AlphaTLB AlphaDTB(const std::string &name, int size); virtual void regStats(); - Fault translate(RequestPtr &req, ExecContext *xc, bool write) const; + Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const; }; #endif // __ALPHA_MEMORY_HH__ diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc index d2d148cc6..82e44b9e7 100644 --- a/src/arch/alpha/tru64/process.cc +++ b/src/arch/alpha/tru64/process.cc @@ -33,7 +33,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/tru64/process.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/tru64/tru64.hh" #include "sim/process.hh" @@ -45,9 +45,9 @@ using namespace AlphaISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<AlphaTru64::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<AlphaTru64::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "OSF1"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -55,43 +55,43 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "732"); strcpy(name->machine, "alpha"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } /// Target getsysyinfo() handler. static SyscallReturn getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + unsigned nbytes = tc->getSyscallArg(2); switch (op) { case AlphaTru64::GSI_MAX_CPU: { - TypedBufferArg<uint32_t> max_cpu(xc->getSyscallArg(1)); + TypedBufferArg<uint32_t> max_cpu(tc->getSyscallArg(1)); *max_cpu = htog((uint32_t)process->numCpus()); - max_cpu.copyOut(xc->getMemPort()); + max_cpu.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_CPUS_IN_BOX: { - TypedBufferArg<uint32_t> cpus_in_box(xc->getSyscallArg(1)); + TypedBufferArg<uint32_t> cpus_in_box(tc->getSyscallArg(1)); *cpus_in_box = htog((uint32_t)process->numCpus()); - cpus_in_box.copyOut(xc->getMemPort()); + cpus_in_box.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_PHYSMEM: { - TypedBufferArg<uint64_t> physmem(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> physmem(tc->getSyscallArg(1)); *physmem = htog((uint64_t)1024 * 1024); // physical memory in KB - physmem.copyOut(xc->getMemPort()); + physmem.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_CPU_INFO: { - TypedBufferArg<AlphaTru64::cpu_info> infop(xc->getSyscallArg(1)); + TypedBufferArg<AlphaTru64::cpu_info> infop(tc->getSyscallArg(1)); infop->current_cpu = htog(0); infop->cpus_in_box = htog(process->numCpus()); @@ -103,30 +103,30 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, infop->cpu_ex_binding = htog(0); infop->mhz = htog(667); - infop.copyOut(xc->getMemPort()); + infop.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_PROC_TYPE: { - TypedBufferArg<uint64_t> proc_type(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> proc_type(tc->getSyscallArg(1)); *proc_type = htog((uint64_t)11); - proc_type.copyOut(xc->getMemPort()); + proc_type.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_PLATFORM_NAME: { - BufferArg bufArg(xc->getSyscallArg(1), nbytes); + BufferArg bufArg(tc->getSyscallArg(1), nbytes); strncpy((char *)bufArg.bufferPtr(), "COMPAQ Professional Workstation XP1000", nbytes); - bufArg.copyOut(xc->getMemPort()); + bufArg.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_CLK_TCK: { - TypedBufferArg<uint64_t> clk_hz(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> clk_hz(tc->getSyscallArg(1)); *clk_hz = htog((uint64_t)1024); - clk_hz.copyOut(xc->getMemPort()); + clk_hz.copyOut(tc->getMemPort()); return 1; } @@ -141,14 +141,14 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target setsysyinfo() handler. static SyscallReturn setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); + unsigned op = tc->getSyscallArg(0); switch (op) { case AlphaTru64::SSI_IEEE_FP_CONTROL: warn("setsysinfo: ignoring ieee_set_fp_control() arg 0x%x\n", - xc->getSyscallArg(1)); + tc->getSyscallArg(1)); break; default: @@ -163,22 +163,22 @@ setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target table() handler. static SyscallReturn tableFunc(SyscallDesc *desc, int callnum,Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace std; using namespace TheISA; - int id = xc->getSyscallArg(0); // table ID - int index = xc->getSyscallArg(1); // index into table + int id = tc->getSyscallArg(0); // table ID + int index = tc->getSyscallArg(1); // index into table // arg 2 is buffer pointer; type depends on table ID - int nel = xc->getSyscallArg(3); // number of elements - int lel = xc->getSyscallArg(4); // expected element size + int nel = tc->getSyscallArg(3); // number of elements + int lel = tc->getSyscallArg(4); // expected element size switch (id) { case AlphaTru64::TBL_SYSINFO: { if (index != 0 || nel != 1 || lel != sizeof(Tru64::tbl_sysinfo)) return -EINVAL; - TypedBufferArg<Tru64::tbl_sysinfo> elp(xc->getSyscallArg(2)); + TypedBufferArg<Tru64::tbl_sysinfo> elp(tc->getSyscallArg(2)); const int clk_hz = one_million; elp->si_user = htog(curTick / (Clock::Frequency / clk_hz)); @@ -190,7 +190,7 @@ SyscallReturn tableFunc(SyscallDesc *desc, int callnum,Process *process, elp->si_phz = htog(clk_hz); elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch? elp->si_max_procs = htog(process->numCpus()); - elp.copyOut(xc->getMemPort()); + elp.copyOut(tc->getMemPort()); return 0; } diff --git a/src/arch/alpha/tru64/system.cc b/src/arch/alpha/tru64/system.cc index 13e5c36db..8d9a53273 100644 --- a/src/arch/alpha/tru64/system.cc +++ b/src/arch/alpha/tru64/system.cc @@ -35,7 +35,7 @@ #include "base/loader/symtab.hh" #include "base/trace.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/tru64/tru64_events.hh" #include "kern/system_events.hh" #include "mem/physical.hh" diff --git a/src/arch/alpha/tru64/system.hh b/src/arch/alpha/tru64/system.hh index 7f64d1042..947e92f50 100644 --- a/src/arch/alpha/tru64/system.hh +++ b/src/arch/alpha/tru64/system.hh @@ -36,7 +36,7 @@ #include "arch/isa_traits.hh" #include "sim/system.hh" -class ExecContext; +class ThreadContext; class BreakPCEvent; class BadAddrEvent; diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index a94742320..ec136091c 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -109,10 +109,10 @@ namespace AlphaISA /** * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void zeroRegisters(XC *xc); + template <class TC> + void zeroRegisters(TC *tc); #if FULL_SYSTEM // Alpha IPR register accessors @@ -143,15 +143,15 @@ namespace AlphaISA RoundPage(Addr addr) { return (addr + PageBytes - 1) & ~(PageBytes - 1); } - void initCPU(ExecContext *xc, int cpuId); - void initIPRs(ExecContext *xc, int cpuId); + void initCPU(ThreadContext *tc, int cpuId); + void initIPRs(ThreadContext *tc, int cpuId); /** * Function to check for and process any interrupts. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void processInterrupts(XC *xc); + template <class TC> + void processInterrupts(TC *tc); #endif } // namespace AlphaISA diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc index 0c69ea0a9..f7fd92c15 100644 --- a/src/arch/alpha/vtophys.cc +++ b/src/arch/alpha/vtophys.cc @@ -36,7 +36,7 @@ #include "arch/alpha/vtophys.hh" #include "base/chunk_generator.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" using namespace std; @@ -85,10 +85,10 @@ AlphaISA::vtophys(Addr vaddr) } Addr -AlphaISA::vtophys(ExecContext *xc, Addr addr) +AlphaISA::vtophys(ThreadContext *tc, Addr addr) { AlphaISA::VAddr vaddr = addr; - Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20); + Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); Addr paddr = 0; //@todo Andrew couldn't remember why he commented some of this code //so I put it back in. Perhaps something to do with gdb debugging? @@ -101,7 +101,7 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) paddr = vaddr; } else { AlphaISA::PageTableEntry pte = - kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr); + kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); if (pte.valid()) paddr = pte.paddr() | vaddr.offset(); } @@ -115,52 +115,52 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) void -AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) +AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) { uint8_t *dst = (uint8_t *)dest; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->readBlob(src, dst, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) +AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) { uint8_t *src = (uint8_t *)source; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->writeBlob(dest, src, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) +AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) { int len = 0; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); do { vp->readBlob(vaddr++, (uint8_t*)dst++, 1); len++; } while (len < maxlen && dst[len] != 0 ); - xc->delVirtPort(vp); + tc->delVirtPort(vp); dst[len] = 0; } void -AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr) +AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) { - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); gen.next()) { vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); src += gen.size(); } - xc->delVirtPort(vp); + tc->delVirtPort(vp); } diff --git a/src/arch/alpha/vtophys.hh b/src/arch/alpha/vtophys.hh index 57782a87a..472c694ff 100644 --- a/src/arch/alpha/vtophys.hh +++ b/src/arch/alpha/vtophys.hh @@ -34,7 +34,7 @@ #include "arch/alpha/isa_traits.hh" -class ExecContext; +class ThreadContext; class FunctionalPort; namespace AlphaISA { @@ -43,12 +43,12 @@ PageTableEntry kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr); Addr vtophys(Addr vaddr); -Addr vtophys(ExecContext *xc, Addr vaddr); +Addr vtophys(ThreadContext *tc, Addr vaddr); -void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len); -void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len); -void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen); -void CopyStringIn(ExecContext *xc, char *src, Addr vaddr); +void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len); +void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len); +void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); }; #endif // __ARCH_ALPHA_VTOPHYS_H__ diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index fa7275908..810c3fed4 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -29,7 +29,7 @@ */ #include "arch/mips/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" @@ -102,28 +102,28 @@ FaultStat IntegerOverflowFault::_count; #if FULL_SYSTEM -void MipsFault::invoke(ExecContext * xc) +void MipsFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); countStat()++; // exception restart address - if (setRestartAddress() || !xc->inPalMode()) - xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC()); + if (setRestartAddress() || !tc->inPalMode()) + tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC()); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - xc->setMiscReg(MipsISA::IPR_EXC_ADDR, - xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); + tc->setMiscReg(MipsISA::IPR_EXC_ADDR, + tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); } - xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); - xc->setNextPC(xc->readPC() + sizeof(MachInst)); + tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); + tc->setNextPC(tc->readPC() + sizeof(MachInst)); } -void ArithmeticFault::invoke(ExecContext * xc) +void ArithmeticFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); panic("Arithmetic traps are unimplemented!"); } diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index 134fa2c4e..d8bf59cc1 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -47,7 +47,7 @@ class MipsFault : public FaultBase virtual bool setRestartAddress() {return true;} public: #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif virtual FaultVect vect() = 0; virtual FaultStat & countStat() = 0; @@ -114,7 +114,7 @@ class ArithmeticFault : public MipsFault FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc index f577a1c94..056c8baff 100644 --- a/src/arch/mips/isa_traits.cc +++ b/src/arch/mips/isa_traits.cc @@ -40,7 +40,7 @@ using namespace std; void -MipsISA::copyRegs(ExecContext *src, ExecContext *dest) +MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) { /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag); uniq = xc->readMiscReg(MipsISA::Uniq_DepTag); @@ -53,7 +53,7 @@ MipsISA::copyRegs(ExecContext *src, ExecContext *dest) } void -MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc) +MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc) { /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag); uniq = xc->readMiscReg(MipsISA::Uniq_DepTag); diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index e99bc7395..dc8b6758a 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -48,7 +48,7 @@ class FastCPU; class FullCPU; class Checkpoint; -class ExecContext; +class ThreadContext; namespace LittleEndianGuest {}; @@ -131,14 +131,14 @@ namespace MipsISA /** * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void zeroRegisters(XC *xc); + template <class TC> + void zeroRegisters(TC *tc); const Addr MaxAddr = (Addr)-1; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); uint64_t fpConvert(double fp_val, ConvertType cvt_type); double roundFP(double val, int digits); diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 1408dbac0..4a919ac27 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -33,7 +33,7 @@ #include "arch/mips/isa_traits.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/linux.hh" #include "sim/process.hh" @@ -45,9 +45,9 @@ using namespace MipsISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -55,7 +55,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "mips"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } @@ -64,18 +64,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, /// different in practice from those used by Tru64 processes. static SyscallReturn sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 45: { // GSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR *fpcr = 0; - fpcr.copyOut(xc->getMemPort()); + fpcr.copyOut(tc->getMemPort()); return 0; } @@ -91,17 +91,17 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target sys_setsysinfo() handler. static SyscallReturn sys_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 14: { // SSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR - fpcr.copyIn(xc->getMemPort()); + fpcr.copyIn(tc->getMemPort()); DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): " " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); return 0; diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index 13d8ac3a8..bd7aa394e 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -34,7 +34,7 @@ #include "arch/mips/linux/process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/builder.hh" #include "sim/system.hh" diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index 3781a91f3..013aa01c7 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -40,7 +40,7 @@ #include "sim/host.hh" class Checkpoint; -class ExecContext; +class ThreadContext; class Regfile; namespace MipsISA diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index 2a0db38a4..dc82a3c26 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -37,7 +37,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; class Regfile; namespace MipsISA diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 72aa17424..f8aeab8cb 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -36,7 +36,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; class Regfile; namespace MipsISA @@ -57,14 +57,14 @@ namespace MipsISA int getInstAsid(); int getDataAsid(); - void copyMiscRegs(ExecContext *xc); + void copyMiscRegs(ThreadContext *tc); MiscReg readReg(int misc_reg) { return miscRegFile[misc_reg]; } - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc) { return miscRegFile[misc_reg]; } @@ -75,7 +75,7 @@ namespace MipsISA } Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc) + ThreadContext *tc) { miscRegFile[misc_reg] = val; return NoFault; } @@ -87,9 +87,9 @@ namespace MipsISA InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs private: - MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } + MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { } - Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } + Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { } #endif friend class RegFile; }; diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index e1b834568..af61e62cd 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -39,7 +39,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; namespace MipsISA { @@ -64,10 +64,10 @@ namespace MipsISA } MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ExecContext *xc) + Fault &fault, ThreadContext *tc) { fault = NoFault; - return miscRegFile.readRegWithEffect(miscReg, fault, xc); + return miscRegFile.readRegWithEffect(miscReg, fault, tc); } Fault setMiscReg(int miscReg, const MiscReg &val) @@ -76,9 +76,9 @@ namespace MipsISA } Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc) + ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, xc); + return miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg) @@ -189,12 +189,12 @@ namespace MipsISA } }; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ExecContext *src, ExecContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); #if FULL_SYSTEM - void copyIprs(ExecContext *src, ExecContext *dest); + void copyIprs(ThreadContext *src, ThreadContext *dest); #endif } // namespace MipsISA diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh index 3516b1d19..38767cef7 100644 --- a/src/arch/mips/stacktrace.hh +++ b/src/arch/mips/stacktrace.hh @@ -34,13 +34,13 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" -class ExecContext; +class ThreadContext; class StackTrace; class ProcessInfo { private: - ExecContext *xc; + ThreadContext *tc; int thread_info_size; int task_struct_size; @@ -49,7 +49,7 @@ class ProcessInfo int name_off; public: - ProcessInfo(ExecContext *_xc); + ProcessInfo(ThreadContext *_tc); Addr task(Addr ksp) const; int pid(Addr ksp) const; @@ -61,7 +61,7 @@ class StackTrace protected: typedef TheISA::MachInst MachInst; private: - ExecContext *xc; + ThreadContext *tc; std::vector<Addr> stack; private: @@ -70,21 +70,21 @@ class StackTrace bool decodeSave(MachInst inst, int ®, int &disp); bool decodeStack(MachInst inst, int &disp); - void trace(ExecContext *xc, bool is_call); + void trace(ThreadContext *tc, bool is_call); public: StackTrace(); - StackTrace(ExecContext *xc, StaticInstPtr inst); + StackTrace(ThreadContext *tc, StaticInstPtr inst); ~StackTrace(); void clear() { - xc = 0; + tc = 0; stack.clear(); } - bool valid() const { return xc != NULL; } - bool trace(ExecContext *xc, StaticInstPtr inst); + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); public: const std::vector<Addr> &getstack() const { return stack; } @@ -106,7 +106,7 @@ class StackTrace }; inline bool -StackTrace::trace(ExecContext *xc, StaticInstPtr inst) +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) { if (!inst->isCall() && !inst->isReturn()) return false; @@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst) if (valid()) clear(); - trace(xc, !inst->isReturn()); + trace(tc, !inst->isReturn()); return true; } diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 09fdf230a..57b4d4d86 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -30,7 +30,7 @@ */ #include "arch/sparc/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" @@ -220,36 +220,36 @@ FaultStat TrapInstruction::_count; #if FULL_SYSTEM -void SparcFault::invoke(ExecContext * xc) +void SparcFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); countStat()++; //Use the SPARC trap state machine /*// exception restart address - if (setRestartAddress() || !xc->inPalMode()) - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc); + if (setRestartAddress() || !tc->inPalMode()) + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, - xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, + tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); } - if (!xc->inPalMode()) - AlphaISA::swap_palshadow(&(xc->regs), true); + if (!tc->inPalMode()) + AlphaISA::swap_palshadow(&(tc->regs), true); - xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); - xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/ + tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); + tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/ } #endif #if !FULL_SYSTEM -void TrapInstruction::invoke(ExecContext * xc) +void TrapInstruction::invoke(ThreadContext * tc) { - xc->syscall(syscall_num); + tc->syscall(syscall_num); } #endif diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 88efe2eee..9f595a28b 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -46,7 +46,7 @@ class SparcFault : public FaultBase { public: #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif virtual TrapType trapType() = 0; virtual FaultPriority priority() = 0; @@ -585,7 +585,7 @@ class TrapInstruction : public EnumeratedFault FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} #if !FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index d4fcbb522..346f7b730 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -36,7 +36,7 @@ #include "config/full_system.hh" #include "sim/host.hh" -class ExecContext; +class ThreadContext; class FastCPU; //class FullCPU; class Checkpoint; diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index db9a32c28..e27255e67 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -35,7 +35,7 @@ #include "arch/sparc/regfile.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/linux.hh" #include "sim/process.hh" @@ -48,9 +48,9 @@ using namespace SparcISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -58,40 +58,40 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "sparc"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } SyscallReturn SparcISA::getresuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc) + Process *p, ThreadContext *tc) { const IntReg id = htog(100); - Addr ruid = xc->getSyscallArg(0); - Addr euid = xc->getSyscallArg(1); - Addr suid = xc->getSyscallArg(2); + Addr ruid = tc->getSyscallArg(0); + Addr euid = tc->getSyscallArg(1); + Addr suid = tc->getSyscallArg(2); //Handle the EFAULT case //Set the ruid if(ruid) { BufferArg ruidBuff(ruid, sizeof(IntReg)); memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg)); - ruidBuff.copyOut(xc->getMemPort()); + ruidBuff.copyOut(tc->getMemPort()); } //Set the euid if(euid) { BufferArg euidBuff(euid, sizeof(IntReg)); memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg)); - euidBuff.copyOut(xc->getMemPort()); + euidBuff.copyOut(tc->getMemPort()); } //Set the suid if(suid) { BufferArg suidBuff(suid, sizeof(IntReg)); memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg)); - suidBuff.copyOut(xc->getMemPort()); + suidBuff.copyOut(tc->getMemPort()); } return 0; } diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh index cd59e4fd2..f4819ba84 100644 --- a/src/arch/sparc/linux/process.hh +++ b/src/arch/sparc/linux/process.hh @@ -61,7 +61,7 @@ class SparcLinuxProcess : public SparcLiveProcess }; SyscallReturn getresuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); } // namespace SparcISA #endif // __ALPHA_LINUX_PROCESS_HH__ diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 4b18dcca9..633c202ca 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -35,7 +35,7 @@ #include "arch/sparc/solaris/process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/page_table.hh" #include "mem/translating_port.hh" #include "sim/builder.hh" @@ -113,27 +113,27 @@ SparcLiveProcess::startup() //From the SPARC ABI //The process runs in user mode - execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); + threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); //Setup default FP state - execContexts[0]->setMiscReg(MISCREG_FSR, 0); + threadContexts[0]->setMiscReg(MISCREG_FSR, 0); - execContexts[0]->setMiscReg(MISCREG_TICK, 0); + threadContexts[0]->setMiscReg(MISCREG_TICK, 0); // /* * Register window management registers */ //No windows contain info from other programs - execContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); //There are no windows to pop - execContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); //All windows are available to save into - execContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); //All windows are "clean" - execContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); //Start with register window 0 - execContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); } m5_auxv_t buildAuxVect(int64_t type, int64_t val) @@ -311,14 +311,14 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); - execContexts[0]->setIntReg(ArgumentReg0, argc); - execContexts[0]->setIntReg(ArgumentReg1, argv_array_base); - execContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); + threadContexts[0]->setIntReg(ArgumentReg0, argc); + threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); Addr prog_entry = objFile->entryPoint(); - execContexts[0]->setPC(prog_entry); - execContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); - execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); + threadContexts[0]->setPC(prog_entry); + threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); + threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); // num_processes++; } diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 2739048eb..aaf1fcf24 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -563,9 +563,9 @@ namespace SparcISA #if FULL_SYSTEM /** Process a tick compare event and generate an interrupt on the cpu if * appropriate. */ - void processTickCompare(ExecContext *xc); - void processSTickCompare(ExecContext *xc); - void processHSTickCompare(ExecContext *xc); + void processTickCompare(ThreadContext *tc); + void processSTickCompare(ThreadContext *tc); + void processHSTickCompare(ThreadContext *tc); typedef CpuEventWrapper<MiscRegFile, &MiscRegFile::processTickCompare> TickCompareEvent; @@ -580,10 +580,10 @@ namespace SparcISA HSTickCompareEvent *hSTickCompare; /** Fullsystem only register version of ReadRegWithEffect() */ - MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ExecContext *xc); + MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); /** Fullsystem only register version of SetRegWithEffect() */ Fault setFSRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc); + ThreadContext * tc); #endif public: @@ -657,7 +657,7 @@ namespace SparcISA * are are readFSRegWithEffect (which is called by readRegWithEffect()). * Checking is done for permission based on state bits in the miscreg * file. */ - MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc); + MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); /** write a value into an either an SE or FS IPR. No checking is done * about SE vs. FS as this is mostly used to copy the regfile. Thus more @@ -671,13 +671,13 @@ namespace SparcISA * Checking is done for permission based on state bits in the miscreg * file. */ Fault setRegWithEffect(int miscReg, - const MiscReg &val, ExecContext * xc); + const MiscReg &val, ThreadContext * tc); void serialize(std::ostream & os); void unserialize(Checkpoint * cp, const std::string & section); - void copyMiscRegs(ExecContext * xc); + void copyMiscRegs(ThreadContext * tc); bool isHyperPriv() { return hpstateFields.hpriv; } bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } @@ -753,9 +753,9 @@ namespace SparcISA } MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ExecContext *xc) + Fault &fault, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, fault, xc); + return miscRegFile.readRegWithEffect(miscReg, fault, tc); } Fault setMiscReg(int miscReg, const MiscReg &val) @@ -764,9 +764,9 @@ namespace SparcISA } Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc) + ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, xc); + return miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg, int width) @@ -853,9 +853,9 @@ namespace SparcISA } }; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ExecContext *src, ExecContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); int InterruptLevel(uint64_t softint); diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index 74f77991d..af0550910 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -33,7 +33,7 @@ #include "arch/sparc/regfile.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/solaris/solaris.hh" #include "sim/process.hh" @@ -46,9 +46,9 @@ using namespace SparcISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Solaris::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Solaris::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "SunOS"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -56,7 +56,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "Generic_118558-21"); strcpy(name->machine, "sun4u"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh index dd86a1553..d12aee211 100644 --- a/src/arch/sparc/stacktrace.hh +++ b/src/arch/sparc/stacktrace.hh @@ -34,13 +34,13 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" -class ExecContext; +class ThreadContext; class StackTrace; class ProcessInfo { private: - ExecContext *xc; + ThreadContext *tc; int thread_info_size; int task_struct_size; @@ -49,7 +49,7 @@ class ProcessInfo int name_off; public: - ProcessInfo(ExecContext *_xc); + ProcessInfo(ThreadContext *_tc); Addr task(Addr ksp) const; int pid(Addr ksp) const; @@ -61,7 +61,7 @@ class StackTrace protected: typedef TheISA::MachInst MachInst; private: - ExecContext *xc; + ThreadContext *tc; std::vector<Addr> stack; private: @@ -70,21 +70,21 @@ class StackTrace bool decodeSave(MachInst inst, int ®, int &disp); bool decodeStack(MachInst inst, int &disp); - void trace(ExecContext *xc, bool is_call); + void trace(ThreadContext *tc, bool is_call); public: StackTrace(); - StackTrace(ExecContext *xc, StaticInstPtr inst); + StackTrace(ThreadContext *tc, StaticInstPtr inst); ~StackTrace(); void clear() { - xc = 0; + tc = 0; stack.clear(); } - bool valid() const { return xc != NULL; } - bool trace(ExecContext *xc, StaticInstPtr inst); + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); public: const std::vector<Addr> &getstack() const { return stack; } @@ -106,7 +106,7 @@ class StackTrace }; inline bool -StackTrace::trace(ExecContext *xc, StaticInstPtr inst) +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) { if (!inst->isCall() && !inst->isReturn()) return false; @@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst) if (valid()) clear(); - trace(xc, !inst->isReturn()); + trace(tc, !inst->isReturn()); return true; } diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 9f4805058..b89d48663 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -32,7 +32,7 @@ Fault SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, - ExecContext *xc) + ThreadContext *tc) { int64_t time; SparcSystem *sys; @@ -47,25 +47,25 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, setReg(miscReg, val); if (newLevel > oldLevel) ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX - //xc->getCpuPtr()->checkInterrupts = true; + //tc->getCpuPtr()->checkInterrupts = true; return NoFault; case MISCREG_SOFTINT_CLR: - return setRegWithEffect(miscReg, ~val & softint, xc); + return setRegWithEffect(miscReg, ~val & softint, tc); case MISCREG_SOFTINT_SET: - return setRegWithEffect(miscReg, val | softint, xc); + return setRegWithEffect(miscReg, val | softint, tc); case MISCREG_TICK_CMPR: if (isNonPriv()) return new PrivilegedOpcode; if (tickCompare == NULL) - tickCompare = new TickCompareEvent(this, xc); + tickCompare = new TickCompareEvent(this, tc); setReg(miscReg, val); if (tick_cmprFields.int_dis && tickCompare.scheduled()) tickCompare.deschedule(); time = tick_cmprFields.tick_cmpr - tickFields.counter; if (!tick_cmprFields.int_dis && time > 0) - tickCompare.schedule(time * xc->getCpuPtr()->cycles(1)); + tickCompare.schedule(time * tc->getCpuPtr()->cycles(1)); return NoFault; case MISCREG_STICK: @@ -73,7 +73,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, return new PrivilegedOpcode; if (isPriv()) return new PrivilegedAction; - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; stickFields.npt = val & Bit64 ? 1 : 0; @@ -83,8 +83,8 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, if (isNonPriv()) return new PrivilegedOpcode; if (sTickCompare == NULL) - sTickCompare = new STickCompareEvent(this, xc); - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + sTickCompare = new STickCompareEvent(this, tc); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); setReg(miscReg, val); if (stick_cmprFields.int_dis && sTickCompare.scheduled()) @@ -98,7 +98,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_PIL: if (FULL_SYSTEM) { setReg(miscReg, val); - //xc->getCpuPtr()->checkInterrupts; + //tc->getCpuPtr()->checkInterrupts; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX return NoFault; } else @@ -127,8 +127,8 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, if (isNonPriv()) return new PrivilegedOpcode; if (hSTickCompare == NULL) - hSTickCompare = new HSTickCompareEvent(this, xc); - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + hSTickCompare = new HSTickCompareEvent(this, tc); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); setReg(miscReg, val); if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) @@ -143,7 +143,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, } MiscReg -MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) +MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) { switch (miscReg) { @@ -166,7 +166,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) fault = new PrivilegedAction; return 0; } - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; case MISCREG_STICK_CMPR: @@ -204,19 +204,19 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) } void -MiscRegFile::processTickCompare(ExecContext *xc) +MiscRegFile::processTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } void -MiscRegFile::processSTickCompare(ExecContext *xc) +MiscRegFile::processSTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } void -MiscRegFile::processHSTickCompare(ExecContext *xc) +MiscRegFile::processHSTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index f75beb04a..f1c071148 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -81,10 +81,10 @@ namespace SparcISA /** * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void zeroRegisters(XC *xc); + template <class TC> + void zeroRegisters(TC *tc); } // namespace SparcISA diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc index 0c69ea0a9..f7fd92c15 100644 --- a/src/arch/sparc/vtophys.cc +++ b/src/arch/sparc/vtophys.cc @@ -36,7 +36,7 @@ #include "arch/alpha/vtophys.hh" #include "base/chunk_generator.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" using namespace std; @@ -85,10 +85,10 @@ AlphaISA::vtophys(Addr vaddr) } Addr -AlphaISA::vtophys(ExecContext *xc, Addr addr) +AlphaISA::vtophys(ThreadContext *tc, Addr addr) { AlphaISA::VAddr vaddr = addr; - Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20); + Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); Addr paddr = 0; //@todo Andrew couldn't remember why he commented some of this code //so I put it back in. Perhaps something to do with gdb debugging? @@ -101,7 +101,7 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) paddr = vaddr; } else { AlphaISA::PageTableEntry pte = - kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr); + kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); if (pte.valid()) paddr = pte.paddr() | vaddr.offset(); } @@ -115,52 +115,52 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) void -AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) +AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) { uint8_t *dst = (uint8_t *)dest; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->readBlob(src, dst, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) +AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) { uint8_t *src = (uint8_t *)source; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->writeBlob(dest, src, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) +AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) { int len = 0; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); do { vp->readBlob(vaddr++, (uint8_t*)dst++, 1); len++; } while (len < maxlen && dst[len] != 0 ); - xc->delVirtPort(vp); + tc->delVirtPort(vp); dst[len] = 0; } void -AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr) +AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) { - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); gen.next()) { vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); src += gen.size(); } - xc->delVirtPort(vp); + tc->delVirtPort(vp); } diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh index d9b1a25c9..bf2b757d6 100644 --- a/src/arch/sparc/vtophys.hh +++ b/src/arch/sparc/vtophys.hh @@ -34,7 +34,7 @@ #include "arch/sparc/isa_traits.hh" -class ExecContext; +class ThreadContext; class FunctionalPort; namespace SparcISA { @@ -43,12 +43,12 @@ PageTableEntry kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr); Addr vtophys(Addr vaddr); -Addr vtophys(ExecContext *xc, Addr vaddr); +Addr vtophys(ThreadContext *tc, Addr vaddr); -void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len); -void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len); -void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen); -void CopyStringIn(ExecContext *xc, char *src, Addr vaddr); +void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len); +void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len); +void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); }; #endif // __ARCH_SPARC_VTOPHYS_H__ |