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-rw-r--r--src/arch/alpha/regfile.hh5
-rw-r--r--src/arch/mips/regfile/regfile.hh5
-rw-r--r--src/arch/sparc/regfile.hh5
-rw-r--r--src/arch/x86/floatregfile.hh5
-rw-r--r--src/arch/x86/floatregs.hh6
-rw-r--r--src/arch/x86/isa/microasm.isa5
-rw-r--r--src/arch/x86/isa/operands.isa3
-rw-r--r--src/arch/x86/isa_traits.hh4
-rw-r--r--src/arch/x86/miscregs.hh5
-rw-r--r--src/arch/x86/regfile.cc10
-rw-r--r--src/arch/x86/regfile.hh2
11 files changed, 51 insertions, 4 deletions
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index b93707181..792a518fb 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -192,6 +192,11 @@ namespace AlphaISA
return reg;
}
+ static inline int flattenFloatIndex(ThreadContext * tc, int reg)
+ {
+ return reg;
+ }
+
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index b83bb576b..4be8d399c 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -187,6 +187,11 @@ namespace MipsISA
return reg;
}
+ static inline int flattenFloatIndex(ThreadContext * tc, int reg)
+ {
+ return reg;
+ }
+
void
copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index f3e253f7e..7972d6982 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -122,6 +122,11 @@ namespace SparcISA
int flattenIntIndex(ThreadContext * tc, int reg);
+ int flattenFloatIndex(ThreadContext * tc, int reg)
+ {
+ return reg;
+ }
+
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh
index 14dda443f..b77ddb0eb 100644
--- a/src/arch/x86/floatregfile.hh
+++ b/src/arch/x86/floatregfile.hh
@@ -101,8 +101,9 @@ namespace X86ISA
std::string getFloatRegName(RegIndex);
//Each 128 bit xmm register is broken into two effective 64 bit registers.
- const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
- const int NumFloatRegs = NumFloatArchRegs;
+ const int NumFloatRegs =
+ NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
+ const int NumFloatArchRegs = NumFloatRegs + 8;
class FloatRegFile
{
diff --git a/src/arch/x86/floatregs.hh b/src/arch/x86/floatregs.hh
index b9d6a5c43..30846ec00 100644
--- a/src/arch/x86/floatregs.hh
+++ b/src/arch/x86/floatregs.hh
@@ -162,6 +162,12 @@ namespace X86ISA
{
return (FloatRegIndex)(FLOATREG_MICROFP_BASE + index);
}
+
+ static inline FloatRegIndex
+ FLOATREG_STACK(int index, int top)
+ {
+ return (FloatRegIndex)(NUM_FLOATREGS + ((top - index + 8) % 8));
+ }
};
#endif // __ARCH_X86_FLOATREGS_HH__
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 579909506..e961cc63c 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -136,5 +136,10 @@ let {{
assembler.symbols["label"] = labeler
+ def stack_index(index):
+ return "(NUM_FLOATREGS + (%s))" % index
+
+ assembler.symbols["st"] = stack_index
+
macroopDict = assembler.assemble(microcode)
}};
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 7b0427b44..05a9f4418 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -115,6 +115,9 @@ def operands {{
'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
+ # The TOP register should needs to be more protected so that later
+ # instructions don't map their indexes with an old value.
+ 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61),
'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 602c99390..f3478d7f6 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -89,7 +89,9 @@ namespace X86ISA
//mmx/x87 registers
8 +
//xmm registers
- 16
+ 16 +
+ //The indices that are mapped over the fp stack
+ 8
};
// semantically meaningful register indices
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index 01499e7ad..bab813719 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -171,9 +171,12 @@ namespace X86ISA
MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
MISCREG_TR_ATTR,
+ // Floating point control registers
+ MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
+
//XXX Add "Model-Specific Registers"
- NUM_MISCREGS = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments
+ NUM_MISCREGS
};
static inline MiscRegIndex
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 96283cada..889f2f5cd 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -85,6 +85,7 @@
* Authors: Gabe Black
*/
+#include "arch/x86/floatregs.hh"
#include "arch/x86/regfile.hh"
#include "base/trace.hh"
#include "sim/serialize.hh"
@@ -218,6 +219,15 @@ int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
return (reg & ~(1 << 6));
}
+int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
+{
+ if (reg > NUM_FLOATREGS) {
+ int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP);
+ reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
+ }
+ return reg;
+}
+
void RegFile::serialize(std::ostream &os)
{
intRegFile.serialize(os);
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index d4425b04c..650181aca 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -149,6 +149,8 @@ namespace X86ISA
int flattenIntIndex(ThreadContext * tc, int reg);
+ int flattenFloatIndex(ThreadContext * tc, int reg);
+
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);