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-rw-r--r--src/arch/arm/isa/insts/ldr64.isa29
-rw-r--r--src/arch/arm/isa/insts/str64.isa6
-rw-r--r--src/arch/arm/isa/operands.isa2
-rw-r--r--src/arch/generic/memhelpers.hh2
-rw-r--r--src/arch/sparc/isa/decoder.isa76
-rw-r--r--src/arch/sparc/isa/includes.isa1
-rw-r--r--src/arch/sparc/isa/operands.isa4
-rw-r--r--src/arch/sparc/types.hh1
-rw-r--r--src/arch/x86/isa/includes.isa1
9 files changed, 58 insertions, 64 deletions
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index eea925e66..e035e1d7e 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -198,14 +198,11 @@ let {{
'''
elif self.size == 16:
accCode = '''
- Twin64_t data = cSwap(Mem%s,
- isBigEndian64(xc->tcBase()));
-
-
- AA64FpDestP0_uw = (uint32_t)data.a;
- AA64FpDestP1_uw = (data.a >> 32);
- AA64FpDestP2_uw = (uint32_t)data.b;
- AA64FpDestP3_uw = (data.b >> 32);
+ auto data = cSwap(Mem%s, isBigEndian64(xc->tcBase()));
+ AA64FpDestP0_uw = (uint32_t)data[0];
+ AA64FpDestP1_uw = (data[0] >> 32);
+ AA64FpDestP2_uw = (uint32_t)data[1];
+ AA64FpDestP3_uw = (data[1] >> 32);
'''
elif self.flavor == "widen" or self.size == 8:
accCode = "XDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));"
@@ -242,12 +239,12 @@ let {{
'''
elif self.size == 8:
accCode = '''
- AA64FpDestP0_uw = (uint32_t)Mem_tud.a;
- AA64FpDestP1_uw = (uint32_t)(Mem_tud.a >> 32);
+ AA64FpDestP0_uw = (uint32_t)Mem_tud[0];
+ AA64FpDestP1_uw = (uint32_t)(Mem_tud[0] >> 32);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
- AA64FpDest2P0_uw = (uint32_t)Mem_tud.b;
- AA64FpDest2P1_uw = (uint32_t)(Mem_tud.b >> 32);
+ AA64FpDest2P0_uw = (uint32_t)Mem_tud[1];
+ AA64FpDest2P1_uw = (uint32_t)(Mem_tud[1] >> 32);
AA64FpDest2P2_uw = 0;
AA64FpDest2P3_uw = 0;
'''
@@ -262,8 +259,8 @@ let {{
'''
elif self.size == 8:
accCode = '''
- XDest = Mem_tud.a;
- XDest2 = Mem_tud.b;
+ XDest = Mem_tud[0];
+ XDest2 = Mem_tud[1];
'''
else:
if self.size == 4:
@@ -275,8 +272,8 @@ let {{
'''
elif self.size == 8:
accCode = '''
- XDest = Mem_tud.a;
- XDest2 = Mem_tud.b;
+ XDest = Mem_tud[0];
+ XDest2 = Mem_tud[1];
'''
self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa
index 0b153c1ec..324d1fc69 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -226,9 +226,9 @@ let {{
accCode = '''
// This temporary needs to be here so that the parser
// will correctly identify this instruction as a store.
- Twin64_t temp;
- temp.a = XDest_ud;
- temp.b = XDest2_ud;
+ std::array<uint64_t, 2> temp;
+ temp[0] = XDest_ud;
+ temp[1] = XDest2_ud;
Mem_tud = temp;
'''
self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 2e2955a80..babf0accf 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -47,7 +47,7 @@ def operand_types {{
'sw' : 'int32_t',
'uw' : 'uint32_t',
'ud' : 'uint64_t',
- 'tud' : 'Twin64_t',
+ 'tud' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
'vc' : 'TheISA::VecRegContainer',
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index a0359a5a7..35e666b92 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -114,7 +114,7 @@ writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
if (fault == NoFault && res != NULL) {
if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
- *res = TheISA::gtoh((MemT)*res);
+ *(MemT *)res = TheISA::gtoh(*(MemT *)res);
else
*res = TheISA::gtoh(*res);
}
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 8c23d5f03..6ca52c406 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1102,8 +1102,8 @@ decode OP default Unknown::unknown()
0x01: ldub({{Rd = Mem_ub;}});
0x02: lduh({{Rd = Mem_uhw;}});
0x03: ldtw({{
- RdLow = (Mem_tuw).a;
- RdHigh = (Mem_tuw).b;
+ RdLow = Mem_tuw[0];
+ RdHigh = Mem_tuw[1];
}});
}
format Store {
@@ -1115,9 +1115,9 @@ decode OP default Unknown::unknown()
// will correctly identify this instruction as a store.
// It's probably either the parenthesis or referencing
// the member variable that throws confuses it.
- Twin32_t temp;
- temp.a = RdLow<31:0>;
- temp.b = RdHigh<31:0>;
+ std::array<uint32_t, 2> temp;
+ temp[0] = RdLow<31:0>;
+ temp[1] = RdHigh<31:0>;
Mem_tuw = temp;
}});
}
@@ -1145,63 +1145,63 @@ decode OP default Unknown::unknown()
0x13: decode EXT_ASI {
// ASI_LDTD_AIUP
0x22: TwinLoad::ldtx_aiup(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTD_AIUS
0x23: TwinLoad::ldtx_aius(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_QUAD_LDD
0x24: TwinLoad::ldtx_quad_ldd(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_REAL
0x26: TwinLoad::ldtx_real(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_N
0x27: TwinLoad::ldtx_n(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_AIUP_L
0x2A: TwinLoad::ldtx_aiup_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_AIUS_L
0x2B: TwinLoad::ldtx_aius_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_L
0x2C: TwinLoad::ldtx_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_REAL_L
0x2E: TwinLoad::ldtx_real_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_N_L
0x2F: TwinLoad::ldtx_n_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_P
0xE2: TwinLoad::ldtx_p(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_S
0xE3: TwinLoad::ldtx_s(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_PL
0xEA: TwinLoad::ldtx_pl(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_SL
0xEB: TwinLoad::ldtx_sl(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
default: ldtwa({{
- RdLow = (Mem_tuw).a;
- RdHigh = (Mem_tuw).b;}});
+ RdLow = Mem_tuw[0];
+ RdHigh = Mem_tuw[1];}});
}
}
format StoreAlt {
@@ -1213,9 +1213,9 @@ decode OP default Unknown::unknown()
// will correctly identify this instruction as a store.
// It's probably either the parenthesis or referencing
// the member variable that throws confuses it.
- Twin32_t temp;
- temp.a = RdLow<31:0>;
- temp.b = RdHigh<31:0>;
+ std::array<uint32_t, 2> temp;
+ temp[0] = RdLow<31:0>;
+ temp[1] = RdHigh<31:0>;
Mem_tuw = temp;
}});
}
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index ff48b0aec..0ff93a873 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -80,7 +80,6 @@ output exec {{
#include "arch/generic/memhelpers.hh"
#include "arch/sparc/asi.hh"
-#include "base/bigint.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/Sparc.hh"
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 32a39bbee..26c0d87a7 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -37,8 +37,8 @@ def operand_types {{
'uw' : 'uint32_t',
'sdw' : 'int64_t',
'udw' : 'uint64_t',
- 'tudw' : 'Twin64_t',
- 'tuw' : 'Twin32_t',
+ 'tudw' : 'std::array<uint64_t, 2>',
+ 'tuw' : 'std::array<uint32_t, 2>',
'sf' : 'float',
'df' : 'double',
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index ec88b9e2c..a0f757df3 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -32,7 +32,6 @@
#define __ARCH_SPARC_TYPES_HH__
#include "arch/generic/types.hh"
-#include "base/bigint.hh"
#include "base/types.hh"
namespace SparcISA
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 1fad1ec1a..715adc9d7 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -115,7 +115,6 @@ output exec {{
#include "arch/x86/faults.hh"
#include "arch/x86/memhelpers.hh"
#include "arch/x86/tlb.hh"
-#include "base/bigint.hh"
#include "base/compiler.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 20:53:53 +0000