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-rw-r--r--src/arch/x86/insts/micromediaop.hh7
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py24
-rw-r--r--src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py18
-rw-r--r--src/arch/x86/isa/microasm.isa2
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa2
5 files changed, 30 insertions, 23 deletions
diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index f2871f67e..7f8e3a364 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -36,6 +36,7 @@
namespace X86ISA
{
enum MediaFlag {
+ MediaMultHiOp = 1,
MediaScalarOp = 128
};
@@ -75,6 +76,12 @@ namespace X86ISA
{
return scalarOp() ? 1 : (sizeof(FloatRegBits) / size);
}
+
+ bool
+ multHi() const
+ {
+ return ext & MediaMultHiOp;
+ }
};
class MediaOpReg : public MediaOpBase
diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py
index 274ee4287..2715f5d25 100644
--- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py
+++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py
@@ -55,23 +55,23 @@
microcode = '''
def macroop PMULHW_XMM_XMM {
- mmuli xmml, xmml, xmmlm, size=2, ext=(0x2 | 0x8)
- mmuli xmmh, xmmh, xmmhm, size=2, ext=(0x2 | 0x8)
+ mmuli xmml, xmml, xmmlm, size=2, ext = "0x2 |" + MultHi
+ mmuli xmmh, xmmh, xmmhm, size=2, ext = "0x2 |" + MultHi
};
def macroop PMULHW_XMM_M {
ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
- mmuli xmml, xmml, ufp1, size=2, ext=(0x2 | 0x8)
- mmuli xmmh, xmmh, ufp2, size=2, ext=(0x2 | 0x8)
+ mmuli xmml, xmml, ufp1, size=2, ext = "0x2 |" + MultHi
+ mmuli xmmh, xmmh, ufp2, size=2, ext = "0x2 |" + MultHi
};
def macroop PMULHW_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
- mmuli xmml, xmml, ufp1, size=2, ext=(0x2 | 0x8)
- mmuli xmmh, xmmh, ufp2, size=2, ext=(0x2 | 0x8)
+ mmuli xmml, xmml, ufp1, size=2, ext = "0x2 |" + MultHi
+ mmuli xmmh, xmmh, ufp2, size=2, ext = "0x2 |" + MultHi
};
def macroop PMULLW_XMM_XMM {
@@ -95,23 +95,23 @@ def macroop PMULLW_XMM_P {
};
def macroop PMULHUW_XMM_XMM {
- mmuli xmml, xmml, xmmlm, size=2, ext=8
- mmuli xmmh, xmmh, xmmhm, size=2, ext=8
+ mmuli xmml, xmml, xmmlm, size=2, ext = MultHi
+ mmuli xmmh, xmmh, xmmhm, size=2, ext = MultHi
};
def macroop PMULHUW_XMM_M {
ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
- mmuli xmml, xmml, ufp1, size=2, ext=8
- mmuli xmmh, xmmh, ufp2, size=2, ext=8
+ mmuli xmml, xmml, ufp1, size=2, ext = MultHi
+ mmuli xmmh, xmmh, ufp2, size=2, ext = MultHi
};
def macroop PMULHUW_XMM_P {
rdip t7
ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
- mmuli xmml, xmml, ufp1, size=2, ext=8
- mmuli xmmh, xmmh, ufp2, size=2, ext=8
+ mmuli xmml, xmml, ufp1, size=2, ext = MultHi
+ mmuli xmmh, xmmh, ufp2, size=2, ext = MultHi
};
def macroop PMULUDQ_XMM_XMM {
diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py
index d116d04b3..50a1e5dc0 100644
--- a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py
+++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py
@@ -55,18 +55,18 @@
microcode = '''
def macroop PMULHW_MMX_MMX {
- mmuli mmx, mmx, mmxm, size=2, ext=(0x2 | 0x8)
+ mmuli mmx, mmx, mmxm, size=2, ext = "0x2 |" + MultHi
};
def macroop PMULHW_MMX_M {
ldfp ufp1, seg, sib, disp, dataSize=8
- mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x8)
+ mmuli mmx, mmx, ufp1, size=2, ext = "0x2 |" + MultHi
};
def macroop PMULHW_MMX_P {
rdip t7
ldfp ufp1, seg, riprel, disp, dataSize=8
- mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x8)
+ mmuli mmx, mmx, ufp1, size=2, ext = "0x2 |" + MultHi
};
def macroop PMULLW_MMX_MMX {
@@ -85,33 +85,33 @@ def macroop PMULLW_MMX_P {
};
def macroop PMULHRW_MMX_MMX {
- mmuli mmx, mmx, mmxm, size=2, ext=(0x2 | 0x4 | 0x8)
+ mmuli mmx, mmx, mmxm, size=2, ext = "0x2 | 0x4 |" + MultHi
};
def macroop PMULHRW_MMX_M {
ldfp ufp1, seg, sib, disp, dataSize=8
- mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x4 | 0x8)
+ mmuli mmx, mmx, ufp1, size=2, ext = "0x2 | 0x4 |" + MultHi
};
def macroop PMULHRW_MMX_P {
rdip t7
ldfp ufp1, seg, riprel, disp, dataSize=8
- mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x4 | 0x8)
+ mmuli mmx, mmx, ufp1, size=2, ext = "0x2 | 0x4 |" + MultHi
};
def macroop PMULHUW_MMX_MMX {
- mmuli mmx, mmx, mmxm, size=2, ext=8
+ mmuli mmx, mmx, mmxm, size=2, ext = MultHi
};
def macroop PMULHUW_MMX_M {
ldfp ufp1, seg, sib, disp, dataSize=8
- mmuli mmx, mmx, ufp1, size=2, ext=8
+ mmuli mmx, mmx, ufp1, size=2, ext = MultHi
};
def macroop PMULHUW_MMX_P {
rdip t7
ldfp ufp1, seg, riprel, disp, dataSize=8
- mmuli mmx, mmx, ufp1, size=2, ext=8
+ mmuli mmx, mmx, ufp1, size=2, ext = MultHi
};
def macroop PMULUDQ_MMX_MMX {
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 23e2f74ca..e48ad3d69 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -181,7 +181,7 @@ let {{
'kernel_gs_base'):
assembler.symbols[reg] = regIdx("MISCREG_%s" % reg.upper())
- for flag in ('Scalar',):
+ for flag in ('Scalar', 'MultHi'):
assembler.symbols[flag] = 'Media%sOp' % flag
# Code literal which forces a default 64 bit operand size in 64 bit mode.
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 0a45e38fb..84d2d7f70 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -1043,7 +1043,7 @@ let {{
if (ext & 0x4)
resBits += (ULL(1) << (destBits - 1));
- if (ext & 0x8)
+ if (multHi())
resBits >>= destBits;
int destHiIndex = (i + 1) * destBits - 1;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 22:56:07 +0000