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-rw-r--r--src/arch/arm/isa/insts/branch.isa6
-rw-r--r--src/arch/arm/isa/insts/data.isa19
-rw-r--r--src/arch/arm/isa/insts/ldr.isa7
-rw-r--r--src/arch/arm/isa/insts/mem.isa10
-rw-r--r--src/arch/arm/isa/templates/branch.isa4
-rw-r--r--src/arch/arm/isa/templates/mem.isa18
-rw-r--r--src/arch/arm/isa/templates/pred.isa13
7 files changed, 65 insertions, 12 deletions
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index 84b9bb720..767c07835 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -81,6 +81,7 @@ let {{
for (mnem, imm, link) in blxList:
Name = mnem.capitalize()
+ isRasPop = 0
if imm:
Name += "Imm"
# Since we're switching ISAs, the target ISA will be the opposite
@@ -123,7 +124,7 @@ let {{
instFlags += ["IsCall"]
else:
linkStr = ""
- instFlags += ["IsReturn"]
+ isRasPop = "op1 == INTREG_LR"
if imm and link: #blx with imm
branchStr = '''
@@ -141,7 +142,8 @@ let {{
"branch": branchStr}
blxIop = InstObjParams(mnem, Name, base,
{"code": code, "brTgtCode" : br_tgt_code,
- "predicate_test": predicateTest}, instFlags)
+ "predicate_test": predicateTest,
+ "is_ras_pop" : isRasPop }, instFlags)
header_output += declare.subst(blxIop)
decoder_output += constructor.subst(blxIop)
exec_output += PredOpExecute.subst(blxIop)
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index ac5b12a95..9af81b465 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -143,7 +143,8 @@ let {{
subst(immIopCc)
def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
- buildCc = True, buildNonCc = True, instFlags = []):
+ buildCc = True, buildNonCc = True, isRasPop = "0", \
+ isBranch = "0", instFlags = []):
cCode = carryCode[flagType]
vCode = overflowCode[flagType]
negBit = 31
@@ -161,13 +162,15 @@ let {{
}
regCode = secondOpRe.sub(regOp2, code)
regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
- {"code" : regCode,
+ {"code" : regCode, "is_ras_pop" : isRasPop,
+ "is_branch" : isBranch,
"predicate_test": predicateTest}, instFlags)
regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
"DataRegOp",
{"code" : regCode + regCcCode,
- "predicate_test": condPredicateTest},
- instFlags)
+ "predicate_test": condPredicateTest,
+ "is_ras_pop" : isRasPop,
+ "is_branch" : isBranch}, instFlags)
def subst(iop):
global header_output, decoder_output, exec_output
@@ -222,7 +225,7 @@ let {{
def buildDataInst(mnem, code, flagType = "logic", \
aiw = True, regRegAiw = True,
- subsPcLr = True):
+ subsPcLr = True, isRasPop = "0", isBranch = "0"):
regRegCode = instCode = code
if aiw:
instCode = "AIW" + instCode
@@ -230,7 +233,8 @@ let {{
regRegCode = "AIW" + regRegCode
buildImmDataInst(mnem, instCode, flagType)
- buildRegDataInst(mnem, instCode, flagType)
+ buildRegDataInst(mnem, instCode, flagType,
+ isRasPop = isRasPop, isBranch = isBranch)
buildRegRegDataInst(mnem, regRegCode, flagType)
if subsPcLr:
code += '''
@@ -269,7 +273,8 @@ let {{
buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
- buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
+ buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False,
+ isRasPop = "op1 == INTREG_LR", isBranch = "dest == INTREG_PC")
buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
buildDataInst("movt",
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 2e45f2875..bfa94103f 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -58,6 +58,7 @@ let {{
self.sign = sign
self.user = user
self.flavor = flavor
+ self.rasPop = False
if self.add:
self.op = " +"
@@ -77,7 +78,7 @@ let {{
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
self.memFlags, instFlags, base,
- wbDecl, pcDecl)
+ wbDecl, pcDecl, self.rasPop)
header_output += newHeader
decoder_output += newDecoder
@@ -128,6 +129,10 @@ let {{
else:
self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
+ if self.add and self.post and self.writeback and not self.sign and \
+ not self.user and self.size == 4:
+ self.rasPop = True
+
class LoadRegInst(LoadInst):
def __init__(self, *args, **kargs):
super(LoadRegInst, self).__init__(*args, **kargs)
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index d0c0f0710..ca0d701d3 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -48,7 +48,8 @@ let {{
self.constructTemplate = eval(self.decConstBase + 'Constructor')
def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
- base = 'Memory', wbDecl = None, pcDecl = None):
+ base = 'Memory', wbDecl = None, pcDecl = None,
+ rasPop = False):
# Make sure flags are in lists (convert to lists if not).
memFlags = makeList(memFlags)
instFlags = makeList(instFlags)
@@ -85,6 +86,10 @@ let {{
codeBlobsCopy['use_uops'] = 0
codeBlobsCopy['use_wb'] = 0
codeBlobsCopy['use_pc'] = 0
+ is_ras_pop = "0"
+ if rasPop:
+ is_ras_pop = "1"
+ codeBlobsCopy['is_ras_pop'] = is_ras_pop
iop = InstObjParams(name, Name, base,
codeBlobsCopy, instFlagsCopy)
@@ -102,7 +107,8 @@ let {{
"acc_name" : Name,
"use_uops" : use_uops,
"use_pc" : use_pc,
- "use_wb" : use_wb },
+ "use_wb" : use_wb,
+ "is_ras_pop" : is_ras_pop },
['IsMacroop'])
header_output += self.declareTemplate.subst(iop)
decoder_output += self.constructTemplate.subst(iop)
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 6abf76963..3a8fbb363 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -120,6 +120,8 @@ def template BranchRegConstructor {{
} else {
flags[IsUncondControl] = true;
}
+ if (%(is_ras_pop)s)
+ flags[IsReturn] = true;
}
}};
@@ -150,6 +152,8 @@ def template BranchRegCondConstructor {{
} else {
flags[IsUncondControl] = true;
}
+ if (%(is_ras_pop)s)
+ flags[IsReturn] = true;
}
}};
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index dcfd47ace..f26ee55e8 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1188,7 +1188,9 @@ def template LoadRegConstructor {{
(IntRegIndex)_index)
{
%(constructor)s;
+ bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
+ conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
@@ -1204,6 +1206,12 @@ def template LoadRegConstructor {{
uops[1] = new %(wb_decl)s;
uops[1]->setDelayedCommit();
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
+ uops[2]->setFlag(StaticInst::IsControl);
+ uops[2]->setFlag(StaticInst::IsIndirectControl);
+ if (conditional)
+ uops[2]->setFlag(StaticInst::IsCondControl);
+ else
+ uops[2]->setFlag(StaticInst::IsUncondControl);
uops[2]->setLastMicroop();
} else if(_dest == _index) {
IntRegIndex wbIndexReg = INTREG_UREG0;
@@ -1234,7 +1242,9 @@ def template LoadImmConstructor {{
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
%(constructor)s;
+ bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
+ conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
@@ -1249,6 +1259,14 @@ def template LoadImmConstructor {{
uops[1] = new %(wb_decl)s;
uops[1]->setDelayedCommit();
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
+ uops[2]->setFlag(StaticInst::IsControl);
+ uops[2]->setFlag(StaticInst::IsIndirectControl);
+ if (conditional)
+ uops[2]->setFlag(StaticInst::IsCondControl);
+ else
+ uops[2]->setFlag(StaticInst::IsUncondControl);
+ if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
+ uops[2]->setFlag(StaticInst::IsReturn);
uops[2]->setLastMicroop();
} else {
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 2a4bd9dab..95c7c8e1b 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -107,6 +107,19 @@ def template DataRegConstructor {{
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
}
+
+ if (%(is_branch)s){
+ flags[IsControl] = true;
+ flags[IsIndirectControl] = true;
+ if (condCode == COND_AL || condCode == COND_UC)
+ flags[IsCondControl] = true;
+ else
+ flags[IsUncondControl] = true;
+ }
+
+ if (%(is_ras_pop)s) {
+ flags[IsReturn] = true;
+ }
}
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 08:08:08 +0000