diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/alpha/process.hh | 9 | ||||
| -rw-r--r-- | src/arch/alpha/system.hh | 6 | ||||
| -rw-r--r-- | src/arch/alpha/tlb.hh | 8 | ||||
| -rw-r--r-- | src/arch/arm/table_walker.hh | 10 | ||||
| -rw-r--r-- | src/arch/arm/tlb.hh | 14 | ||||
| -rw-r--r-- | src/arch/generic/tlb.hh | 2 |
6 files changed, 24 insertions, 25 deletions
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh index cd45871b1..fcaa6539c 100644 --- a/src/arch/alpha/process.hh +++ b/src/arch/alpha/process.hh @@ -43,16 +43,17 @@ class AlphaLiveProcess : public LiveProcess AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile); void loadState(CheckpointIn &cp) override; - void initState(); + void initState() override; void argsInit(int intSize, int pageSize); public: - AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i); + AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; /// Explicitly import the otherwise hidden getSyscallArg using LiveProcess::getSyscallArg; - void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val); - void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); + void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override; + void setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) override; }; /* No architectural page table defined for this ISA */ diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh index f8ca54506..d0be46135 100644 --- a/src/arch/alpha/system.hh +++ b/src/arch/alpha/system.hh @@ -55,7 +55,7 @@ class AlphaSystem : public System /** * Initialise the state of the system. */ - virtual void initState(); + void initState() override; /** * Serialization stuff @@ -65,7 +65,7 @@ class AlphaSystem : public System /** Override startup() to provide a path to call setupFuncEvents() */ - virtual void startup(); + void startup() override; /** * Set the m5AlphaAccess pointer in the console @@ -121,7 +121,7 @@ class AlphaSystem : public System return addFuncEvent<T>(consoleSymtab, lbl); } - virtual Addr fixFuncEventAddr(Addr addr); + Addr fixFuncEventAddr(Addr addr) override; public: void setIntrFreq(Tick freq) { intrFreq = freq; } diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index a8bdf30e1..b9b6228e2 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -85,21 +85,21 @@ class TLB : public BaseTLB TLB(const Params *p); virtual ~TLB(); - void takeOverFrom(BaseTLB *otlb) {} + void takeOverFrom(BaseTLB *otlb) override {} - virtual void regStats(); + void regStats() override; int getsize() const { return table.size(); } TlbEntry &index(bool advance = true); void insert(Addr vaddr, TlbEntry &entry); - void flushAll(); + void flushAll() override; void flushProcesses(); void flushAddr(Addr addr, uint8_t asn); void - demapPage(Addr vaddr, uint64_t asn) + demapPage(Addr vaddr, uint64_t asn) override { assert(asn < (1 << 8)); flushAddr(vaddr, asn); diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 8af70075d..b960c320b 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -884,7 +884,7 @@ class TableWalker : public MemObject return dynamic_cast<const Params *>(_params); } - virtual void init(); + void init() override; bool haveLPAE() const { return _haveLPAE; } bool haveVirtualization() const { return _haveVirtualization; } @@ -892,12 +892,12 @@ class TableWalker : public MemObject /** Checks if all state is cleared and if so, completes drain */ void completeDrain(); DrainState drain() override; - virtual void drainResume() override; + void drainResume() override; - virtual BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + BaseMasterPort& getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) override; - void regStats(); + void regStats() override; Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index f6776b0a9..1f9ec01ec 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -155,10 +155,10 @@ class TLB : public BaseTLB virtual ~TLB(); - void takeOverFrom(BaseTLB *otlb); + void takeOverFrom(BaseTLB *otlb) override; /// setup all the back pointers - virtual void init(); + void init() override; TableWalker *getTableWalker() { return tableWalker; } @@ -197,7 +197,7 @@ class TLB : public BaseTLB /** Reset the entire TLB. Used for CPU switching to prevent stale * translations after multiple switches */ - void flushAll() + void flushAll() override { flushAllSecurity(false, 0, true); flushAllSecurity(true, 0, true); @@ -230,14 +230,12 @@ class TLB : public BaseTLB void printTlb() const; - void demapPage(Addr vaddr, uint64_t asn) + void demapPage(Addr vaddr, uint64_t asn) override { // needed for x86 only panic("demapPage() is not implemented.\n"); } - static bool validVirtualAddress(Addr vaddr); - /** * Do a functional lookup on the TLB (for debugging) * and don't modify any internal state @@ -290,7 +288,7 @@ class TLB : public BaseTLB void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; - void regStats(); + void regStats() override; void regProbePoints() override; @@ -304,7 +302,7 @@ class TLB : public BaseTLB * * @return A pointer to the walker master port */ - virtual BaseMasterPort* getMasterPort(); + BaseMasterPort* getMasterPort() override; // Caching misc register values here. // Writing to misc registers needs to invalidate them. diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh index 0a7e78151..995fbfff4 100644 --- a/src/arch/generic/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -123,7 +123,7 @@ class GenericTLB : public BaseTLB {} public: - void demapPage(Addr vaddr, uint64_t asn); + void demapPage(Addr vaddr, uint64_t asn) override; Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); void translateTiming(RequestPtr req, ThreadContext *tc, |