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-rw-r--r--src/arch/SConscript3
-rw-r--r--src/arch/alpha/isa.hh7
-rw-r--r--src/arch/alpha/registers.hh7
-rw-r--r--src/arch/alpha/utility.cc3
-rw-r--r--src/arch/arm/insts/static_inst.cc2
-rw-r--r--src/arch/arm/isa.hh7
-rw-r--r--src/arch/arm/registers.hh7
-rw-r--r--src/arch/arm/utility.cc11
-rwxr-xr-xsrc/arch/isa_parser.py81
-rw-r--r--src/arch/mips/isa.hh7
-rw-r--r--src/arch/mips/registers.hh7
-rw-r--r--src/arch/null/registers.hh1
-rw-r--r--src/arch/power/insts/static_inst.cc2
-rw-r--r--src/arch/power/isa.hh7
-rw-r--r--src/arch/power/registers.hh7
-rw-r--r--src/arch/power/utility.cc3
-rw-r--r--src/arch/sparc/isa.hh7
-rw-r--r--src/arch/sparc/registers.hh10
-rw-r--r--src/arch/sparc/utility.cc3
-rw-r--r--src/arch/x86/insts/static_inst.cc4
-rw-r--r--src/arch/x86/isa.hh6
-rw-r--r--src/arch/x86/registers.hh5
-rw-r--r--src/arch/x86/utility.cc2
23 files changed, 187 insertions, 12 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript
index b4f94a65f..e7d74ce51 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -135,5 +135,6 @@ env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
DebugFlag('IntRegs')
DebugFlag('FloatRegs')
+DebugFlag('CCRegs')
DebugFlag('MiscRegs')
-CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index e2e2daba8..d30499066 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -103,6 +103,13 @@ namespace AlphaISA
return reg;
}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
+
const Params *params() const;
ISA(Params *p);
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 92ba22ee8..3fd774cf7 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -53,6 +53,9 @@ typedef uint64_t FloatRegBits;
// control register file contents
typedef uint64_t MiscReg;
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
union AnyReg
{
IntReg intreg;
@@ -91,6 +94,7 @@ const int NumFloatArchRegs = 32;
const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
+const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs =
@@ -101,7 +105,8 @@ enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
FP_Reg_Base = NumIntRegs,
- Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
};
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 32fc0b141..2dfe00f96 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -71,6 +71,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
for (int i = 0; i < NumFloatRegs; ++i)
dest->setFloatRegBits(i, src->readFloatRegBits(i));
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 3ab7dfb0e..2a8dee162 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -239,6 +239,8 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
assert(rel_reg < NUM_MISCREGS);
ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
break;
+ case CCRegClass:
+ panic("printReg: CCRegClass but ARM has no CC regs\n");
}
}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index e7abb26b2..6fd57549a 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -140,6 +140,13 @@ namespace ArmISA
return reg;
}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
+
int
flattenMiscIndex(int reg)
{
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index cc4fac824..b9033fd5b 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -68,6 +68,9 @@ typedef float FloatReg;
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
@@ -76,6 +79,7 @@ const int NumFloatSpecialRegs = 8;
const int NumIntRegs = NUM_INTREGS;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
@@ -102,7 +106,8 @@ const int SyscallSuccessReg = ReturnValueReg;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
-const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 776c1ae82..cddc2c5c4 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -113,7 +113,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
void
skipFunction(ThreadContext *tc)
{
- TheISA::PCState newPC = tc->pcState();
+ PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
CheckerCPU *checker = tc->getCheckerCpuPtr();
@@ -127,13 +127,16 @@ skipFunction(ThreadContext *tc)
void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
- for (int i = 0; i < TheISA::NumIntRegs; i++)
+ for (int i = 0; i < NumIntRegs; i++)
dest->setIntRegFlat(i, src->readIntRegFlat(i));
- for (int i = 0; i < TheISA::NumFloatRegs; i++)
+ for (int i = 0; i < NumFloatRegs; i++)
dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
- for (int i = 0; i < TheISA::NumMiscRegs; i++)
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
+ for (int i = 0; i < NumMiscRegs; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
// setMiscReg "with effect" will set the misc register mapping correctly.
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index e4f81c173..dd9f2e873 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1,4 +1,5 @@
# Copyright (c) 2003-2005 The Regents of The University of Michigan
+# Copyright (c) 2013 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -497,6 +498,9 @@ class Operand(object):
def isIntReg(self):
return 0
+ def isCCReg(self):
+ return 0
+
def isControlReg(self):
return 0
@@ -660,6 +664,79 @@ class FloatRegOperand(Operand):
}''' % (self.ctype, self.base_name, wp)
return wb
+class CCRegOperand(Operand):
+ def isReg(self):
+ return 1
+
+ def isCCReg(self):
+ return 1
+
+ def makeConstructor(self, predRead, predWrite):
+ c_src = ''
+ c_dest = ''
+
+ if self.is_src:
+ c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + CC_Reg_Base;' % \
+ (self.reg_spec)
+ if self.hasReadPred():
+ c_src = '\n\tif (%s) {%s\n\t}' % \
+ (self.read_predicate, c_src)
+
+ if self.is_dest:
+ c_dest = \
+ '\n\t_destRegIdx[_numDestRegs++] = %s + CC_Reg_Base;' % \
+ (self.reg_spec)
+ c_dest += '\n\t_numCCDestRegs++;'
+ if self.hasWritePred():
+ c_dest = '\n\tif (%s) {%s\n\t}' % \
+ (self.write_predicate, c_dest)
+
+ return c_src + c_dest
+
+ def makeRead(self, predRead):
+ if (self.ctype == 'float' or self.ctype == 'double'):
+ error('Attempt to read condition-code register as FP')
+ if self.read_code != None:
+ return self.buildReadCode('readCCRegOperand')
+
+ int_reg_val = ''
+ if predRead:
+ int_reg_val = 'xc->readCCRegOperand(this, _sourceIndex++)'
+ if self.hasReadPred():
+ int_reg_val = '(%s) ? %s : 0' % \
+ (self.read_predicate, int_reg_val)
+ else:
+ int_reg_val = 'xc->readCCRegOperand(this, %d)' % self.src_reg_idx
+
+ return '%s = %s;\n' % (self.base_name, int_reg_val)
+
+ def makeWrite(self, predWrite):
+ if (self.ctype == 'float' or self.ctype == 'double'):
+ error('Attempt to write condition-code register as FP')
+ if self.write_code != None:
+ return self.buildWriteCode('setCCRegOperand')
+
+ if predWrite:
+ wp = 'true'
+ if self.hasWritePred():
+ wp = self.write_predicate
+
+ wcond = 'if (%s)' % (wp)
+ windex = '_destIndex++'
+ else:
+ wcond = ''
+ windex = '%d' % self.dest_reg_idx
+
+ wb = '''
+ %s
+ {
+ %s final_val = %s;
+ xc->setCCRegOperand(this, %s, final_val);\n
+ if (traceData) { traceData->setData(final_val); }
+ }''' % (wcond, self.ctype, self.base_name, windex)
+
+ return wb
+
class ControlRegOperand(Operand):
def isReg(self):
return 1
@@ -815,6 +892,7 @@ class OperandList(object):
self.numDestRegs = 0
self.numFPDestRegs = 0
self.numIntDestRegs = 0
+ self.numCCDestRegs = 0
self.numMiscDestRegs = 0
self.memOperand = None
@@ -835,6 +913,8 @@ class OperandList(object):
self.numFPDestRegs += 1
elif op_desc.isIntReg():
self.numIntDestRegs += 1
+ elif op_desc.isCCReg():
+ self.numCCDestRegs += 1
elif op_desc.isControlReg():
self.numMiscDestRegs += 1
elif op_desc.isMem():
@@ -1030,6 +1110,7 @@ class InstObjParams(object):
header += '\n\t_numDestRegs = 0;'
header += '\n\t_numFPDestRegs = 0;'
header += '\n\t_numIntDestRegs = 0;'
+ header += '\n\t_numCCDestRegs = 0;'
self.constructor = header + \
self.operands.concatAttrStrings('constructor')
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 04d4a1dfa..c601cfc1e 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -177,6 +177,13 @@ namespace MipsISA
{
return reg;
}
+
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
};
}
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index d9d94e47b..0ac84cc7f 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -54,6 +54,7 @@ const int NumFloatSpecialRegs = 5;
const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+const int NumCCRegs = 0;
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
@@ -276,7 +277,8 @@ const int NumMiscRegs = MISCREG_NUMREGS;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
-const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
@@ -292,6 +294,9 @@ typedef float FloatReg;
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
typedef union {
IntReg intreg;
FloatReg fpreg;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index f33b7e5bd..1e52fc5a6 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -47,6 +47,7 @@ namespace NullISA {
typedef uint64_t IntReg;
typedef uint32_t FloatRegBits;
typedef float FloatReg;
+typedef uint8_t CCReg;
typedef uint64_t MiscReg;
}
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index 09b662453..087e1f740 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -55,6 +55,8 @@ PowerStaticInst::printReg(std::ostream &os, int reg) const
default: ccprintf(os, "unknown_reg");
break;
}
+ case CCRegClass:
+ panic("printReg: POWER does not implement CCRegClass\n");
}
}
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 33439c48c..7b59b2ad1 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -98,6 +98,13 @@ class ISA : public SimObject
return reg;
}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
+
void startup(ThreadContext *tc) {}
/// Explicitly import the otherwise hidden startup
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 89de3719c..abee516fc 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -52,6 +52,9 @@ typedef uint64_t FloatRegBits;
typedef double FloatReg;
typedef uint64_t MiscReg;
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
@@ -64,6 +67,7 @@ const int NumInternalProcRegs = 0;
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
// Semantically meaningful register indices
@@ -85,7 +89,8 @@ const int SyscallSuccessReg = 3;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
-const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index e3fa246fc..7be195b8d 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -48,6 +48,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
for (int i = 0; i < NumFloatRegs; ++i)
dest->setFloatRegBits(i, src->readFloatRegBits(i));
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 86092f3b5..e6f023bc0 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -206,6 +206,13 @@ class ISA : public SimObject
return reg;
}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
+
typedef SparcISAParams Params;
const Params *params() const;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 0e774b69e..b25f34584 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -48,6 +48,10 @@ typedef uint64_t IntReg;
typedef uint64_t MiscReg;
typedef float FloatReg;
typedef uint32_t FloatRegBits;
+
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
typedef union
{
IntReg intReg;
@@ -70,14 +74,16 @@ const int SyscallPseudoReturnReg = 9;
const int NumIntArchRegs = 32;
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+const int NumCCRegs = 0;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
FP_Reg_Base = NumIntRegs,
- Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
- Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
+ CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
+ Max_Reg_Index = Misc_Reg_Base + NumMiscRegs,
};
} // namespace SparcISA
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index d99ef4aa0..9fa102c6a 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -234,6 +234,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
dest->setFloatRegBits(i, src->readFloatRegBits(i));
}
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index 046a11fb6..39091289f 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -221,6 +221,10 @@ namespace X86ISA
break;
}
+ case CCRegClass:
+ ccprintf(os, "%%cc%d", rel_reg);
+ break;
+
case MiscRegClass:
switch (rel_reg) {
default:
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 3ccc2f0ad..5f36fd7ad 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -85,6 +85,12 @@ namespace X86ISA
return reg;
}
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void startup(ThreadContext *tc);
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index bb9f5f7b1..d62992dcd 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -57,6 +57,7 @@ const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs =
NumIntArchRegs + NumMicroIntRegs +
NumPseudoIntRegs + NumImplicitIntRegs;
+const int NumCCRegs = 0;
// Each 128 bit xmm register is broken into two effective 64 bit registers.
// Add 8 for the indices that are mapped over the fp stack
@@ -69,7 +70,8 @@ enum DependenceTags {
// register index which has the IntFoldBit (1 << 6) set. To be safe
// we just start at (1 << 7) == 128.
FP_Reg_Base = 128,
- Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
};
@@ -87,6 +89,7 @@ const int FramePointerReg = INTREG_RBP;
const int SyscallPseudoReturnReg = INTREG_RDX;
typedef uint64_t IntReg;
+typedef uint64_t CCReg;
//XXX Should this be a 128 bit structure for XMM memory ops?
typedef uint64_t LargestRead;
typedef uint64_t MiscReg;
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index b50b99dfa..df7d3935d 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -244,6 +244,8 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
//copy float regs
for (int i = 0; i < NumFloatRegs; ++i)
dest->setFloatRegBits(i, src->readFloatRegBits(i));
+ // Will need to add condition-code regs when implemented
+ assert(NumCCRegs == 0);
copyMiscRegs(src, dest);
dest->pcState(src->pcState());
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 07:48:50 +0000