diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/alpha/tlb.cc | 10 | ||||
| -rw-r--r-- | src/arch/alpha/tlb.hh | 2 |
2 files changed, 9 insertions, 3 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 77bf5e285..4f960360e 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -116,7 +116,7 @@ TLB::lookup(Addr vpn, uint8_t asn) Fault -TLB::checkCacheability(RequestPtr &req) +TLB::checkCacheability(RequestPtr &req, bool itb) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address @@ -148,6 +148,12 @@ TLB::checkCacheability(RequestPtr &req) req->setPaddr(req->getPaddr() & PAddrUncachedMask); #endif } + // We shouldn't be able to read from an uncachable address in Alpha as + // we don't have a ROM and we don't want to try to fetch from a device + // register as we destroy any data that is clear-on-read. + if (req->isUncacheable() && itb) + return new UnimpFault("CPU trying to fetch from uncached I/O"); + } return NoFault; } @@ -390,7 +396,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) if (req->getPaddr() & ~PAddrImplMask) return genMachineCheckFault(); - return checkCacheability(req); + return checkCacheability(req, true); } diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index e61ae5c6d..f94d06ccd 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -92,7 +92,7 @@ namespace AlphaISA return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); } - static Fault checkCacheability(RequestPtr &req); + static Fault checkCacheability(RequestPtr &req, bool itb = false); // Checkpointing virtual void serialize(std::ostream &os); |