diff options
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/process.cc | 4 | ||||
-rw-r--r-- | src/arch/sparc/faults.cc | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 4e9f1e9dd..669f7da80 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -179,7 +179,7 @@ void AlphaLiveProcess::setupASNReg() { ThreadContext *tc = system->getThreadContext(contextIds[0]); - tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); + tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57); } @@ -187,7 +187,7 @@ void AlphaLiveProcess::loadState(CheckpointIn &cp) { LiveProcess::loadState(cp); - // need to set up ASN after unserialization since M5_pid value may + // need to set up ASN after unserialization since _pid value may // come from checkpoint setupASNReg(); } diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index c181e3021..27a928f48 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -630,7 +630,7 @@ FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, } else { Addr alignedVaddr = p->pTable->pageAlign(vaddr); tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/, - p->M5_pid /*context id*/, false, entry.pte); + p->_pid /*context id*/, false, entry.pte); } } @@ -654,7 +654,7 @@ FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst) } else { Addr alignedVaddr = p->pTable->pageAlign(vaddr); tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/, - p->M5_pid /*context id*/, false, entry.pte); + p->_pid /*context id*/, false, entry.pte); } } |