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-rw-r--r--src/arch/alpha/AlphaSystem.py4
-rw-r--r--src/arch/alpha/SConscript41
-rw-r--r--src/arch/alpha/ev5.cc17
-rw-r--r--src/arch/alpha/faults.cc108
-rw-r--r--src/arch/alpha/faults.hh13
-rw-r--r--src/arch/alpha/isa/decoder.isa76
-rw-r--r--src/arch/alpha/isa/fp.isa2
-rw-r--r--src/arch/alpha/isa/main.isa2
-rw-r--r--src/arch/alpha/isa_traits.hh1
-rw-r--r--src/arch/alpha/linux/system.cc3
-rw-r--r--src/arch/alpha/pagetable.hh1
-rw-r--r--src/arch/alpha/predecoder.hh7
-rw-r--r--src/arch/alpha/regredir.cc9
-rw-r--r--src/arch/alpha/remote_gdb.cc88
-rw-r--r--src/arch/alpha/system.cc2
-rw-r--r--src/arch/alpha/system.hh5
-rw-r--r--src/arch/alpha/tlb.cc3
-rw-r--r--src/arch/alpha/utility.cc36
-rw-r--r--src/arch/alpha/utility.hh3
-rw-r--r--src/arch/arm/ArmTLB.py22
-rw-r--r--src/arch/arm/SConscript29
-rw-r--r--src/arch/arm/faults.cc79
-rw-r--r--src/arch/arm/faults.hh17
-rw-r--r--src/arch/arm/insts/static_inst.hh7
-rw-r--r--src/arch/arm/isa/formats/data.isa2
-rw-r--r--src/arch/arm/isa/formats/m5ops.isa8
-rw-r--r--src/arch/arm/isa/formats/unimp.isa9
-rw-r--r--src/arch/arm/isa/insts/div.isa18
-rw-r--r--src/arch/arm/isa/insts/m5ops.isa5
-rw-r--r--src/arch/arm/isa/insts/misc.isa51
-rw-r--r--src/arch/arm/isa/insts/neon.isa41
-rw-r--r--src/arch/arm/isa/insts/swap.isa9
-rw-r--r--src/arch/arm/pagetable.hh1
-rw-r--r--src/arch/arm/remote_gdb.cc48
-rw-r--r--src/arch/arm/tlb.cc65
-rw-r--r--src/arch/arm/tlb.hh5
-rw-r--r--src/arch/arm/utility.cc87
-rwxr-xr-xsrc/arch/mips/BISystem.py11
-rw-r--r--src/arch/mips/MipsSystem.py26
-rw-r--r--src/arch/mips/SConscript35
-rwxr-xr-xsrc/arch/mips/dsp.cc1
-rwxr-xr-xsrc/arch/mips/dsp.hh1
-rw-r--r--src/arch/mips/faults.cc7
-rw-r--r--src/arch/mips/faults.hh7
-rwxr-xr-xsrc/arch/mips/interrupts.cc1
-rw-r--r--src/arch/mips/isa/decoder.isa10
-rw-r--r--src/arch/mips/isa/formats/control.isa8
-rwxr-xr-xsrc/arch/mips/isa/formats/dsp.isa4
-rw-r--r--src/arch/mips/isa/formats/fp.isa4
-rw-r--r--src/arch/mips/isa/formats/unimp.isa6
-rw-r--r--src/arch/mips/isa/includes.isa2
-rw-r--r--src/arch/mips/isa_traits.hh2
-rw-r--r--src/arch/mips/linux/system.cc17
-rwxr-xr-xsrc/arch/mips/pagetable.hh53
-rw-r--r--src/arch/mips/remote_gdb.cc10
-rw-r--r--src/arch/mips/stacktrace.cc1
-rwxr-xr-xsrc/arch/mips/system.cc7
-rwxr-xr-xsrc/arch/mips/system.hh7
-rw-r--r--src/arch/mips/tlb.cc185
-rw-r--r--src/arch/mips/tlb.hh27
-rw-r--r--src/arch/mips/utility.cc24
-rw-r--r--src/arch/mips/utility.hh2
-rwxr-xr-xsrc/arch/mips/vtophys.cc19
-rw-r--r--src/arch/mips/vtophys.hh18
-rw-r--r--src/arch/power/PowerInterrupts.py33
-rw-r--r--src/arch/power/SConscript13
-rw-r--r--src/arch/power/interrupts.cc (renamed from src/arch/mips/mips_core_specific.hh)21
-rw-r--r--src/arch/power/interrupts.hh105
-rw-r--r--src/arch/power/kernel_stats.hh52
-rw-r--r--src/arch/power/pagetable.hh1
-rw-r--r--src/arch/power/stacktrace.cc131
-rw-r--r--src/arch/power/tlb.cc17
-rw-r--r--src/arch/power/utility.cc13
-rw-r--r--src/arch/power/utility.hh4
-rwxr-xr-xsrc/arch/power/vtophys.cc (renamed from src/arch/mips/mips_core_specific.cc)33
-rw-r--r--src/arch/power/vtophys.hh3
-rw-r--r--src/arch/sparc/SConscript32
-rw-r--r--src/arch/sparc/faults.cc128
-rw-r--r--src/arch/sparc/faults.hh19
-rw-r--r--src/arch/sparc/isa.cc30
-rw-r--r--src/arch/sparc/isa.hh5
-rw-r--r--src/arch/sparc/isa/base.isa2
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa2
-rw-r--r--src/arch/sparc/isa/includes.isa1
-rw-r--r--src/arch/sparc/isa_traits.hh4
-rw-r--r--src/arch/sparc/mmapped_ipr.hh9
-rw-r--r--src/arch/sparc/pagetable.hh1
-rw-r--r--src/arch/sparc/remote_gdb.cc26
-rw-r--r--src/arch/sparc/tlb.cc33
-rw-r--r--src/arch/sparc/tlb.hh5
-rw-r--r--src/arch/sparc/ua2005.cc5
-rw-r--r--src/arch/sparc/utility.cc28
-rw-r--r--src/arch/sparc/utility.hh7
-rw-r--r--src/arch/x86/SConscript41
-rw-r--r--src/arch/x86/X86LocalApic.py2
-rw-r--r--src/arch/x86/X86TLB.py17
-rw-r--r--src/arch/x86/bios/SConscript27
-rw-r--r--src/arch/x86/faults.cc151
-rw-r--r--src/arch/x86/faults.hh10
-rw-r--r--src/arch/x86/interrupts.cc10
-rw-r--r--src/arch/x86/interrupts.hh3
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa4
-rw-r--r--src/arch/x86/isa/includes.isa1
-rw-r--r--src/arch/x86/mmapped_ipr.hh9
-rw-r--r--src/arch/x86/remote_gdb.cc1
-rw-r--r--src/arch/x86/tlb.cc132
-rw-r--r--src/arch/x86/tlb.hh12
-rw-r--r--src/arch/x86/utility.cc17
-rw-r--r--src/arch/x86/utility.hh18
-rw-r--r--src/arch/x86/vtophys.cc7
111 files changed, 1258 insertions, 1388 deletions
diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
index f6d9eb4c6..fcbe81edd 100644
--- a/src/arch/alpha/AlphaSystem.py
+++ b/src/arch/alpha/AlphaSystem.py
@@ -27,6 +27,7 @@
# Authors: Nathan Binkert
from m5.params import *
+from m5.proxy import *
from System import System
class AlphaSystem(System):
@@ -42,6 +43,9 @@ class LinuxAlphaSystem(AlphaSystem):
system_type = 34
system_rev = 1 << 10
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ "boot processor frequency")
+
class FreebsdAlphaSystem(AlphaSystem):
type = 'FreebsdAlphaSystem'
system_type = 34
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index e3701d2a4..7e683364a 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -34,40 +34,33 @@ Import('*')
if env['TARGET_ISA'] == 'alpha':
Source('ev5.cc')
Source('faults.cc')
+ Source('freebsd/system.cc')
+ Source('idle_event.cc')
+ Source('interrupts.cc')
Source('ipr.cc')
Source('isa.cc')
+ Source('kernel_stats.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
+ Source('osfpal.cc')
Source('pagetable.cc')
+ Source('process.cc')
Source('regredir.cc')
Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
Source('tlb.cc')
+ Source('tru64/process.cc')
+ Source('tru64/system.cc')
+ Source('tru64/tru64.cc')
Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('AlphaInterrupts.py')
+ SimObject('AlphaSystem.py')
SimObject('AlphaTLB.py')
- if env['FULL_SYSTEM']:
- SimObject('AlphaInterrupts.py')
- SimObject('AlphaSystem.py')
-
- Source('idle_event.cc')
- Source('interrupts.cc')
- Source('kernel_stats.cc')
- Source('osfpal.cc')
- Source('stacktrace.cc')
- Source('system.cc')
- Source('vtophys.cc')
-
- Source('freebsd/system.cc')
- Source('linux/system.cc')
- Source('tru64/system.cc')
-
- else:
- Source('process.cc')
-
- Source('linux/linux.cc')
- Source('linux/process.cc')
-
- Source('tru64/tru64.cc')
- Source('tru64/process.cc')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 6259f8fc2..4dcc58ffe 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -36,7 +36,6 @@
#include "arch/alpha/tlb.hh"
#include "base/cp_annotate.hh"
#include "base/debug.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
@@ -44,8 +43,6 @@
namespace AlphaISA {
-#if FULL_SYSTEM
-
////////////////////////////////////////////////////////////////////////
//
// Machine dependent functions
@@ -76,8 +73,6 @@ zeroRegisters(CPU *cpu)
cpu->thread->setFloatReg(ZeroReg, 0.0);
}
-#endif
-
////////////////////////////////////////////////////////////////////////
//
//
@@ -201,10 +196,8 @@ ISA::readIpr(int idx, ThreadContext *tc)
return retval;
}
-#ifdef DEBUG
// Cause the simulator to break when changing to the following IPL
int break_ipl = -1;
-#endif
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
@@ -260,10 +253,8 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
case IPR_PALtemp23:
// write entire quad w/ no side-effect
-#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->context(ipr[idx], val, tc);
-#endif
ipr[idx] = val;
break;
@@ -291,14 +282,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
-#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->swpipl(ipr[idx]);
-#endif
break;
case IPR_DTB_CM:
-#if FULL_SYSTEM
if (val & 0x18) {
if (tc->getKernelStats())
tc->getKernelStats()->mode(Kernel::user, tc);
@@ -306,7 +294,6 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
if (tc->getKernelStats())
tc->getKernelStats()->mode(Kernel::kernel, tc);
}
-#endif
case IPR_ICM:
// only write two mode bits - processor mode
@@ -483,8 +470,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
} // namespace AlphaISA
-#if FULL_SYSTEM
-
using namespace AlphaISA;
Fault
@@ -534,5 +519,3 @@ SimpleThread::simPalCheck(int palFunc)
return true;
}
-
-#endif // FULL_SYSTEM
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index c66c6f8ab..a6d3ef2d0 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -35,11 +35,9 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
namespace AlphaISA {
@@ -107,12 +105,12 @@ FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
-#if FULL_SYSTEM
-
void
AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
countStat()++;
PCState pc = tc->pcState();
@@ -135,32 +133,36 @@ void
ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
panic("Arithmetic traps are unimplemented!");
}
void
DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // Set fault address and flags. Even though we're modeling an
- // EV5, we use the EV6 technique of not latching fault registers
- // on VPTE loads (instead of locking the registers until IPR_VA is
- // read, like the EV5). The EV6 approach is cleaner and seems to
- // work with EV5 PAL code, but not the other way around.
- if (!tc->misspeculating() &&
- reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
- // set VA register with faulting address
- tc->setMiscRegNoEffect(IPR_VA, vaddr);
-
- // set MM_STAT register flags
- MachInst machInst = inst->machInst;
- tc->setMiscRegNoEffect(IPR_MM_STAT,
- (((Opcode(machInst) & 0x3f) << 11) |
- ((Ra(machInst) & 0x1f) << 6) |
- (flags & 0x3f)));
-
- // set VA_FORM register with faulting formatted address
- tc->setMiscRegNoEffect(IPR_VA_FORM,
- tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+ if (FullSystem) {
+ // Set fault address and flags. Even though we're modeling an
+ // EV5, we use the EV6 technique of not latching fault registers
+ // on VPTE loads (instead of locking the registers until IPR_VA is
+ // read, like the EV5). The EV6 approach is cleaner and seems to
+ // work with EV5 PAL code, but not the other way around.
+ if (!tc->misspeculating() &&
+ reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+ // set VA register with faulting address
+ tc->setMiscRegNoEffect(IPR_VA, vaddr);
+
+ // set MM_STAT register flags
+ MachInst machInst = inst->machInst;
+ tc->setMiscRegNoEffect(IPR_MM_STAT,
+ (((Opcode(machInst) & 0x3f) << 11) |
+ ((Ra(machInst) & 0x1f) << 6) |
+ (flags & 0x3f)));
+
+ // set VA_FORM register with faulting formatted address
+ tc->setMiscRegNoEffect(IPR_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+ }
}
AlphaFault::invoke(tc);
@@ -169,49 +171,55 @@ DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
void
ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (!tc->misspeculating()) {
- tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
- tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
- tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+ if (FullSystem) {
+ if (!tc->misspeculating()) {
+ tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+ tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+ }
}
AlphaFault::invoke(tc);
}
-#else
-
void
ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(pc, entry);
- if (!success) {
- panic("Tried to execute unmapped address %#x.\n", pc);
+ if (FullSystem) {
+ ItbFault::invoke(tc);
} else {
- VAddr vaddr(pc);
- tc->getITBPtr()->insert(vaddr.page(), entry);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(pc, entry);
+ if (!success) {
+ panic("Tried to execute unmapped address %#x.\n", pc);
+ } else {
+ VAddr vaddr(pc);
+ tc->getITBPtr()->insert(vaddr.page(), entry);
+ }
}
}
void
NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, entry);
- }
- if (!success) {
- panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
+ if (FullSystem) {
+ DtbFault::invoke(tc, inst);
} else {
- tc->getDTBPtr()->insert(vaddr.page(), entry);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ if (p->fixupStackFault(vaddr))
+ success = p->pTable->lookup(vaddr, entry);
+ }
+ if (!success) {
+ panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
+ } else {
+ tc->getDTBPtr()->insert(vaddr.page(), entry);
+ }
}
}
-#endif
-
} // namespace AlphaISA
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 3da97ccb4..7eddd14eb 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -33,7 +33,6 @@
#define __ARCH_ALPHA_FAULTS_HH__
#include "arch/alpha/pagetable.hh"
-#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
@@ -49,10 +48,8 @@ class AlphaFault : public FaultBase
virtual bool skipFaultingInstruction() {return false;}
virtual bool setRestartAddress() {return true;}
public:
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
};
@@ -111,10 +108,8 @@ class ArithmeticFault : public AlphaFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class InterruptFault : public AlphaFault
@@ -147,10 +142,8 @@ class DtbFault : public AlphaFault
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class NDtbMissFault : public DtbFault
@@ -167,10 +160,8 @@ class NDtbMissFault : public DtbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class PDtbMissFault : public DtbFault
@@ -247,10 +238,8 @@ class ItbFault : public AlphaFault
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class ItbPageFault : public ItbFault
@@ -265,10 +254,8 @@ class ItbPageFault : public ItbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class ItbAcvFault : public ItbFault
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 106290784..4bbf83cce 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -202,8 +202,8 @@ decode OPCODE default Unknown::unknown() {
0x6c: decode RA {
31: decode IMM {
1: decode INTIMM {
- // return EV5 for FULL_SYSTEM and EV6 otherwise
- 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
+ // return EV5 for FullSystem and EV6 otherwise
+ 1: implver({{ Rc = FullSystem ? 1 : 2 }});
}
}
}
@@ -780,7 +780,7 @@ decode OPCODE default Unknown::unknown() {
* the parser to understand that.
*/
uint64_t unused_var M5_VAR_USED = Rb;
- Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
+ Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
}}, IsUnverifiable);
// All of the barrier instructions below do nothing in
@@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
- 0xe000: decode FULL_SYSTEM {
+ 0xe000: decode FullSystem {
0: FailUnimpl::rc_se();
default: BasicOperate::rc({{
Ra = IntrFlag;
IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable);
}
- 0xf000: decode FULL_SYSTEM {
+ 0xf000: decode FullSystem {
0: FailUnimpl::rs_se();
default: BasicOperate::rs({{
Ra = IntrFlag;
@@ -821,43 +821,41 @@ decode OPCODE default Unknown::unknown() {
}
}
-#if FULL_SYSTEM
- 0x00: CallPal::call_pal({{
- if (!palValid ||
- (palPriv
- && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
- // invalid pal function code, or attempt to do privileged
- // PAL call in non-kernel mode
- fault = new UnimplementedOpcodeFault;
- } else {
- // check to see if simulator wants to do something special
- // on this PAL call (including maybe suppress it)
- bool dopal = xc->simPalCheck(palFunc);
-
- if (dopal) {
- xc->setMiscReg(IPR_EXC_ADDR, NPC);
- NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+ 0x00: decode FullSystem {
+ 0: decode PALFUNC {
+ format EmulatedCallPal {
+ 0x00: halt ({{
+ exitSimLoop("halt instruction encountered");
+ }}, IsNonSpeculative);
+ 0x83: callsys({{
+ xc->syscall(R0);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
+ // Read uniq reg into ABI return value register (r0)
+ 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
+ // Write uniq reg with value from ABI arg register (r16)
+ 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
}
}
- }}, IsNonSpeculative);
-#else
- 0x00: decode PALFUNC {
- format EmulatedCallPal {
- 0x00: halt ({{
- exitSimLoop("halt instruction encountered");
- }}, IsNonSpeculative);
- 0x83: callsys({{
- xc->syscall(R0);
- }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
- // Read uniq reg into ABI return value register (r0)
- 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
- // Write uniq reg with value from ABI arg register (r16)
- 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
- }
+ default: CallPal::call_pal({{
+ if (!palValid ||
+ (palPriv
+ && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
+ // invalid pal function code, or attempt to do privileged
+ // PAL call in non-kernel mode
+ fault = new UnimplementedOpcodeFault;
+ } else {
+ // check to see if simulator wants to do something special
+ // on this PAL call (including maybe suppress it)
+ bool dopal = xc->simPalCheck(palFunc);
+
+ if (dopal) {
+ xc->setMiscReg(IPR_EXC_ADDR, NPC);
+ NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+ }
+ }
+ }}, IsNonSpeculative);
}
-#endif
-#if FULL_SYSTEM
0x1b: decode PALMODE {
0: OpcdecFault::hw_st_quad();
1: decode HW_LDST_QUAD {
@@ -924,8 +922,6 @@ decode OPCODE default Unknown::unknown() {
}
}
-#endif
-
format BasicOperate {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index e3a6b18ab..5821ebcc5 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -45,7 +45,7 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+ if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault;
}
return fault;
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 796c5e38e..e87a184c3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -64,6 +64,7 @@ output decoder {{
#include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+#include "sim/full_system.hh"
using namespace AlphaISA;
}};
@@ -81,6 +82,7 @@ output exec {{
#include "cpu/exetrace.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 852de5554..97cb845bf 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -36,7 +36,6 @@ namespace LittleEndianGuest {}
#include "arch/alpha/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace AlphaISA {
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 6ca603a3b..e662ef9ce 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -49,7 +49,6 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Thread.hh"
-#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
#include "mem/physical.hh"
@@ -164,7 +163,7 @@ LinuxAlphaSystem::setDelayLoop(ThreadContext *tc)
Addr addr = 0;
if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
Tick cpuFreq = tc->getCpuPtr()->frequency();
- Tick intrFreq = platform->intrFrequency();
+ assert(intrFreq);
VirtualPort *vp;
vp = tc->getVirtPort();
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 59df93bef..b9091d5b6 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -34,7 +34,6 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/utility.hh"
-#include "config/full_system.hh"
namespace AlphaISA {
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index a8788051f..a08cddaec 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -34,7 +34,7 @@
#include "arch/alpha/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
+#include "sim/full_system.hh"
class ThreadContext;
@@ -83,9 +83,8 @@ class Predecoder
{
ext_inst = inst;
emiIsReady = true;
-#if FULL_SYSTEM
- ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
-#endif
+ if (FullSystem)
+ ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
}
bool
diff --git a/src/arch/alpha/regredir.cc b/src/arch/alpha/regredir.cc
index 991138f11..861ded4d1 100644
--- a/src/arch/alpha/regredir.cc
+++ b/src/arch/alpha/regredir.cc
@@ -31,22 +31,13 @@
*/
#include "arch/alpha/regredir.hh"
-#include "config/full_system.hh"
namespace AlphaISA {
-#if FULL_SYSTEM
const int reg_redir[NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
-#else
-const int reg_redir[NumIntRegs] = {
- /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
- /* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
- /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
- /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
-#endif
} // namespace AlphaISA
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index 88d453754..4b285e7ec 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -121,15 +121,12 @@
#include <string>
-#include "config/full_system.hh"
-#if FULL_SYSTEM
-#include "arch/alpha/vtophys.hh"
-#endif
#include "arch/alpha/kgdb.h"
#include "arch/alpha/regredir.hh"
#include "arch/alpha/remote_gdb.hh"
#include "arch/alpha/utility.hh"
+#include "arch/alpha/vtophys.hh"
#include "base/intmath.hh"
#include "base/remote_gdb.hh"
#include "base/socket.hh"
@@ -142,6 +139,7 @@
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace AlphaISA;
@@ -158,51 +156,51 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
bool
RemoteGDB::acc(Addr va, size_t len)
{
-#if !FULL_SYSTEM
- panic("acc function needs to be rewritten for SE mode\n");
-#else
- Addr last_va;
-
- va = TruncPage(va);
- last_va = RoundPage(va + len);
-
- do {
- if (IsK0Seg(va)) {
- if (va < (K0SegBase + pmem->size())) {
- DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
- "%#x < K0SEG + size\n", va);
+ if (FullSystem) {
+ Addr last_va;
+
+ va = TruncPage(va);
+ last_va = RoundPage(va + len);
+
+ do {
+ if (IsK0Seg(va)) {
+ if (va < (K0SegBase + pmem->size())) {
+ DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
+ "%#x < K0SEG + size\n", va);
+ return true;
+ } else {
+ DPRINTF(GDBAcc, "acc: Mapping invalid %#x "
+ "> K0SEG + size\n", va);
+ return false;
+ }
+ }
+
+ /**
+ * This code says that all accesses to palcode (instruction
+ * and data) are valid since there isn't a va->pa mapping
+ * because palcode is accessed physically. At some point this
+ * should probably be cleaned up but there is no easy way to
+ * do it.
+ */
+
+ if (PcPAL(va) || va < 0x10000)
return true;
- } else {
- DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n",
- va);
+
+ Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
+ PageTableEntry pte =
+ kernel_pte_lookup(context->getPhysPort(), ptbr, va);
+ if (!pte.valid()) {
+ DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
return false;
}
- }
-
- /**
- * This code says that all accesses to palcode (instruction
- * and data) are valid since there isn't a va->pa mapping
- * because palcode is accessed physically. At some point this
- * should probably be cleaned up but there is no easy way to
- * do it.
- */
-
- if (PcPAL(va) || va < 0x10000)
- return true;
-
- Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
- PageTableEntry pte =
- kernel_pte_lookup(context->getPhysPort(), ptbr, va);
- if (!pte.valid()) {
- DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
- return false;
- }
- va += PageBytes;
- } while (va < last_va);
+ va += PageBytes;
+ } while (va < last_va);
- DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
- return true;
-#endif
+ DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
+ return true;
+ } else {
+ panic("acc function needs to be rewritten for SE mode\n");
+ }
}
/*
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index 6a55ef8ae..f1afda76e 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -46,7 +46,7 @@
using namespace AlphaISA;
AlphaSystem::AlphaSystem(Params *p)
- : System(p)
+ : System(p), intrFreq(0)
{
consoleSymtab = new SymbolTable;
palSymtab = new SymbolTable;
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index da42ab263..a74aa206f 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -79,6 +79,8 @@ class AlphaSystem : public System
#endif
protected:
+ Tick intrFreq;
+
const Params *params() const { return (const Params *)_params; }
/** Add a function-based event to PALcode. */
@@ -98,6 +100,9 @@ class AlphaSystem : public System
}
virtual Addr fixFuncEventAddr(Addr addr);
+
+ public:
+ void setIntrFreq(Tick freq) { intrFreq = freq; }
};
#endif // __ARCH_ALPHA_SYSTEM_HH__
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index b211c4923..623eafb8a 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -42,6 +42,7 @@
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
+#include "sim/full_system.hh"
using namespace std;
@@ -370,7 +371,7 @@ Fault
TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
- if (FULL_SYSTEM && PcPAL(req->getPC()))
+ if (FullSystem && PcPAL(req->getPC()))
req->setFlags(Request::PHYSICAL);
if (PcPAL(req->getPC())) {
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 5d40f85d7..0048e43e9 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -30,35 +30,33 @@
*/
#include "arch/alpha/utility.hh"
-
-#if FULL_SYSTEM
#include "arch/alpha/vtophys.hh"
#include "mem/vport.hh"
-#endif
+#include "sim/full_system.hh"
namespace AlphaISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
- const int NumArgumentRegs = 6;
- if (number < NumArgumentRegs) {
- if (fp)
- return tc->readFloatRegBits(16 + number);
- else
- return tc->readIntReg(16 + number);
+ if (FullSystem) {
+ const int NumArgumentRegs = 6;
+ if (number < NumArgumentRegs) {
+ if (fp)
+ return tc->readFloatRegBits(16 + number);
+ else
+ return tc->readIntReg(16 + number);
+ } else {
+ Addr sp = tc->readIntReg(StackPointerReg);
+ VirtualPort *vp = tc->getVirtPort();
+ uint64_t arg = vp->read<uint64_t>(sp +
+ (number-NumArgumentRegs) * sizeof(uint64_t));
+ return arg;
+ }
} else {
- Addr sp = tc->readIntReg(StackPointerReg);
- VirtualPort *vp = tc->getVirtPort();
- uint64_t arg = vp->read<uint64_t>(sp +
- (number-NumArgumentRegs) * sizeof(uint64_t));
- return arg;
+ panic("getArgument() is Full system only\n");
+ M5_DUMMY_RETURN;
}
-#else
- panic("getArgument() is Full system only\n");
- M5_DUMMY_RETURN;
-#endif
}
void
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index c0c985c34..a9b5c4cba 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -36,7 +36,6 @@
#include "arch/alpha/registers.hh"
#include "arch/alpha/types.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "arch/alpha/ev5.hh"
@@ -96,9 +95,7 @@ RoundPage(Addr addr)
{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
void initIPRs(ThreadContext *tc, int cpuId);
-#if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId);
-#endif
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index f0d23445f..fc6f51d84 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -37,26 +37,22 @@
#
# Authors: Ali Saidi
-from m5.defines import buildEnv
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
+from MemObject import MemObject
-if buildEnv['FULL_SYSTEM']:
- from MemObject import MemObject
-
- class ArmTableWalker(MemObject):
- type = 'ArmTableWalker'
- cxx_class = 'ArmISA::TableWalker'
- port = Port("Port for TableWalker to do walk the translation with")
- sys = Param.System(Parent.any, "system object parameter")
- min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
- max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
+class ArmTableWalker(MemObject):
+ type = 'ArmTableWalker'
+ cxx_class = 'ArmISA::TableWalker'
+ port = Port("Port for TableWalker to do walk the translation with")
+ sys = Param.System(Parent.any, "system object parameter")
+ min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
+ max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
class ArmTLB(SimObject):
type = 'ArmTLB'
cxx_class = 'ArmISA::TLB'
size = Param.Int(64, "TLB size")
- if buildEnv['FULL_SYSTEM']:
- walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
+ walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index a907e52fb..171c04718 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -54,35 +54,32 @@ if env['TARGET_ISA'] == 'arm':
Source('insts/pred_inst.cc')
Source('insts/static_inst.cc')
Source('insts/vfp.cc')
+ Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
Source('miscregs.cc')
- Source('predecoder.cc')
Source('nativetrace.cc')
+ Source('predecoder.cc')
+ Source('process.cc')
+ Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
+ Source('table_walker.cc')
Source('tlb.cc')
Source('utility.cc')
- Source('remote_gdb.cc')
+ Source('vtophys.cc')
+ SimObject('ArmInterrupts.py')
SimObject('ArmNativeTrace.py')
+ SimObject('ArmSystem.py')
SimObject('ArmTLB.py')
DebugFlag('Arm')
DebugFlag('TLBVerbose')
DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
DebugFlag('Predecoder', "Instructions returned by the predecoder")
- if env['FULL_SYSTEM']:
- Source('interrupts.cc')
- Source('stacktrace.cc')
- Source('system.cc')
- Source('vtophys.cc')
- Source('linux/system.cc')
- Source('table_walker.cc')
-
- SimObject('ArmInterrupts.py')
- SimObject('ArmSystem.py')
- else:
- Source('process.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 68c5fa0e8..52441e03f 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -47,6 +47,7 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
+#include "sim/full_system.hh"
namespace ArmISA
{
@@ -94,13 +95,13 @@ ArmFault::getVector(ThreadContext *tc)
}
-#if FULL_SYSTEM
-
void
ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
// ARM ARM B1.6.3
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
countStat()++;
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
@@ -165,48 +166,54 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
void
Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- tc->getCpuPtr()->clearInterrupts();
- tc->clearArchRegs();
+ if (FullSystem) {
+ tc->getCpuPtr()->clearInterrupts();
+ tc->clearArchRegs();
+ }
ArmFault::invoke(tc, inst);
}
-#else
-
void
UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // If the mnemonic isn't defined this has to be an unknown instruction.
- assert(unknown || mnemonic != NULL);
- if (disabled) {
- panic("Attempted to execute disabled instruction "
- "'%s' (inst 0x%08x)", mnemonic, machInst);
- } else if (unknown) {
- panic("Attempted to execute unknown instruction (inst 0x%08x)",
- machInst);
+ if (FullSystem) {
+ ArmFault::invoke(tc, inst);
} else {
- panic("Attempted to execute unimplemented instruction "
- "'%s' (inst 0x%08x)", mnemonic, machInst);
+ // If the mnemonic isn't defined this has to be an unknown instruction.
+ assert(unknown || mnemonic != NULL);
+ if (disabled) {
+ panic("Attempted to execute disabled instruction "
+ "'%s' (inst 0x%08x)", mnemonic, machInst);
+ } else if (unknown) {
+ panic("Attempted to execute unknown instruction (inst 0x%08x)",
+ machInst);
+ } else {
+ panic("Attempted to execute unimplemented instruction "
+ "'%s' (inst 0x%08x)", mnemonic, machInst);
+ }
}
}
void
SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // As of now, there isn't a 32 bit thumb version of this instruction.
- assert(!machInst.bigThumb);
- uint32_t callNum;
- callNum = tc->readIntReg(INTREG_R7);
- tc->syscall(callNum);
-
- // Advance the PC since that won't happen automatically.
- PCState pc = tc->pcState();
- assert(inst);
- inst->advancePC(pc);
- tc->pcState(pc);
+ if (FullSystem) {
+ ArmFault::invoke(tc, inst);
+ } else {
+ // As of now, there isn't a 32 bit thumb version of this instruction.
+ assert(!machInst.bigThumb);
+ uint32_t callNum;
+ callNum = tc->readIntReg(INTREG_R7);
+ tc->syscall(callNum);
+
+ // Advance the PC since that won't happen automatically.
+ PCState pc = tc->pcState();
+ assert(inst);
+ inst->advancePC(pc);
+ tc->pcState(pc);
+ }
}
-#endif // FULL_SYSTEM
-
template<class T>
void
AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
@@ -245,13 +252,13 @@ template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
void
ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
DPRINTF(Faults, "Invoking ArmSev Fault\n");
-#if FULL_SYSTEM
- // Set sev_mailbox to 1, clear the pending interrupt from remote
- // SEV execution and let pipeline continue as pcState is still
- // valid.
- tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
- tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
-#endif
+ if (FullSystem) {
+ // Set sev_mailbox to 1, clear the pending interrupt from remote
+ // SEV execution and let pipeline continue as pcState is still
+ // valid.
+ tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
+ }
}
// return via SUBS pc, lr, xxx; rfe, movs, ldm
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 2d025cc94..9858e52ef 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -48,8 +48,8 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
@@ -108,10 +108,8 @@ class ArmFault : public FaultBase
FaultStat count;
};
-#if FULL_SYSTEM
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
virtual FaultStat& countStat() = 0;
virtual FaultOffset offset() = 0;
virtual OperatingMode nextMode() = 0;
@@ -139,19 +137,14 @@ class ArmFaultVals : public ArmFault
};
class Reset : public ArmFaultVals<Reset>
-#if FULL_SYSTEM
{
public:
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
-#else
-{};
-#endif //FULL_SYSTEM
class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
{
-#if !FULL_SYSTEM
protected:
ExtMachInst machInst;
bool unknown;
@@ -167,25 +160,27 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
mnemonic(_mnemonic), disabled(_disabled)
{
}
+ UndefinedInstruction() :
+ machInst(0), unknown(false), mnemonic("undefined"), disabled(false)
+ {}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class SupervisorCall : public ArmFaultVals<SupervisorCall>
{
-#if !FULL_SYSTEM
protected:
ExtMachInst machInst;
public:
SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
{}
+ SupervisorCall() : machInst(0)
+ {}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
template <class T>
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index fa850190f..d65555822 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -46,6 +46,7 @@
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "sim/full_system.hh"
namespace ArmISA
{
@@ -294,11 +295,11 @@ class ArmStaticInst : public StaticInst
inline Fault
disabledFault() const
{
-#if FULL_SYSTEM
+ if (FullSystem) {
return new UndefinedInstruction();
-#else
+ } else {
return new UndefinedInstruction(machInst, false, mnemonic, true);
-#endif
+ }
}
};
}
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 03a585001..ffe5f45e3 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1103,7 +1103,6 @@ def format ArmMisc() {{
switch (IMM) {
case 0x0:
return new NopInst(machInst);
-#if FULL_SYSTEM
case 0x1:
return new YieldInst(machInst);
case 0x2:
@@ -1112,7 +1111,6 @@ def format ArmMisc() {{
return new WfiInst(machInst);
case 0x4:
return new SevInst(machInst);
-#endif
default:
return new Unknown(machInst);
}
diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa
index f532d828b..3b08acad7 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -42,35 +42,27 @@ def format M5ops() {{
{
const uint32_t m5func = bits(machInst, 23, 16);
switch(m5func) {
-#if FULL_SYSTEM
case 0x00: return new Arm(machInst);
case 0x01: return new Quiesce(machInst);
case 0x02: return new QuiesceNs(machInst);
case 0x03: return new QuiesceCycles(machInst);
case 0x04: return new QuiesceTime(machInst);
-#endif
case 0x07: return new Rpns(machInst);
case 0x09: return new WakeCPU(machInst);
case 0x10: return new Deprecated_ivlb(machInst);
case 0x11: return new Deprecated_ivle(machInst);
case 0x20: return new Deprecated_exit (machInst);
case 0x21: return new M5exit(machInst);
-#if FULL_SYSTEM
case 0x31: return new Loadsymbol(machInst);
case 0x30: return new Initparam(machInst);
-#endif
case 0x40: return new Resetstats(machInst);
case 0x41: return new Dumpstats(machInst);
case 0x42: return new Dumpresetstats(machInst);
case 0x43: return new M5checkpoint(machInst);
-#if FULL_SYSTEM
case 0x50: return new M5readfile(machInst);
-#endif
case 0x51: return new M5break(machInst);
case 0x52: return new M5switchcpu(machInst);
-#if FULL_SYSTEM
case 0x53: return new M5addsymbol(machInst);
-#endif
case 0x54: return new M5panic(machInst);
case 0x5a: return new M5workbegin(machInst);
case 0x5b: return new M5workend(machInst);
diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa
index a0e0afd32..1c9a4b402 100644
--- a/src/arch/arm/isa/formats/unimp.isa
+++ b/src/arch/arm/isa/formats/unimp.isa
@@ -147,11 +147,10 @@ output exec {{
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(machInst, false, mnemonic);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(machInst, false, mnemonic);
}
Fault
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index 8a94d1ebd..1ff6ef9e4 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -41,11 +41,10 @@ let {{
sdivCode = '''
if (Op2_sw == 0) {
if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
}
Dest_sw = 0;
} else if (Op1_sw == INT_MIN && Op2_sw == -1) {
@@ -65,11 +64,10 @@ let {{
udivCode = '''
if (Op2_uw == 0) {
if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
}
Dest_uw = 0;
} else {
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index 3b837cba9..a157b414c 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -190,12 +190,7 @@ let {{
exec_output += PredOpExecute.subst(loadsymbolIop)
initparamCode = '''
-#if FULL_SYSTEM
Rt = PseudoInst::initParam(xc->tcBase());
-#else
- PseudoInst::panicFsOnlyPseudoInst("initparam");
- Rt = 0;
-#endif
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 870f037d0..b671843cf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,11 +40,11 @@
let {{
svcCode = '''
-#if FULL_SYSTEM
- fault = new SupervisorCall;
-#else
- fault = new SupervisorCall(machInst);
-#endif
+ if (FullSystem) {
+ fault = new SupervisorCall;
+ } else {
+ fault = new SupervisorCall(machInst);
+ }
'''
svcIop = InstObjParams("svc", "Svc", "PredOp",
@@ -502,7 +502,6 @@ let {{
exec_output += PredOpExecute.subst(yieldIop)
wfeCode = '''
-#if FULL_SYSTEM
// WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
if (SevMailbox == 1) {
SevMailbox = 0;
@@ -512,14 +511,11 @@ let {{
} else {
PseudoInst::quiesce(xc->tcBase());
}
-#endif
'''
wfePredFixUpCode = '''
-#if FULL_SYSTEM
// WFE is predicated false, reset SevMailbox to reduce spurious sleeps
// and SEV interrupts
SevMailbox = 1;
-#endif
'''
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
{ "code" : wfeCode,
@@ -531,14 +527,12 @@ let {{
exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
wfiCode = '''
-#if FULL_SYSTEM
// WFI doesn't sleep if interrupts are pending (masked or not)
if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
PseudoInst::quiesceSkip(xc->tcBase());
} else {
PseudoInst::quiesce(xc->tcBase());
}
-#endif
'''
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
@@ -548,7 +542,6 @@ let {{
exec_output += QuiescePredOpExecute.subst(wfiIop)
sevCode = '''
-#if FULL_SYSTEM
SevMailbox = 1;
System *sys = xc->tcBase()->getSystemPtr();
for (int x = 0; x < sys->numContexts(); x++) {
@@ -561,7 +554,6 @@ let {{
oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
}
}
-#endif
'''
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
{ "code" : sevCode, "predicate_test" : predicateTest },
@@ -578,11 +570,10 @@ let {{
decoder_output += BasicConstructor.subst(itIop)
exec_output += PredOpExecute.subst(itIop)
unknownCode = '''
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(machInst, true);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(machInst, true);
'''
unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
{ "code": unknownCode,
@@ -635,12 +626,12 @@ let {{
mrc15code = '''
CPSR cpsr = Cpsr;
- if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (cpsr.mode == MODE_USER) {
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
+ }
Dest = MiscOp1;
'''
@@ -654,12 +645,12 @@ let {{
mcr15code = '''
CPSR cpsr = Cpsr;
- if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (cpsr.mode == MODE_USER) {
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
+ }
MiscDest = Op1;
'''
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index dd0d49a5c..b1ad1eeb3 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -872,11 +872,10 @@ let {{
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
} else {
for (unsigned i = 0; i < eCount; i++) {
Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -927,11 +926,10 @@ let {{
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
} else {
for (unsigned i = 0; i < eCount; i++) {
Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -980,11 +978,10 @@ let {{
readDestCode = 'destReg = destRegs[i];'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
} else {
for (unsigned i = 0; i < rCount; i++) {
FloatReg srcReg1 = srcRegs1[i];
@@ -3296,14 +3293,14 @@ let {{
destReg.elements[i] = srcReg1.elements[index];
} else {
index -= eCount;
- if (index >= eCount)
-#if FULL_SYSTEM
- fault = new UndefinedInstruction;
-#else
- fault = new UndefinedInstruction(false, mnemonic);
-#endif
- else
+ if (index >= eCount) {
+ if (FullSystem)
+ fault = new UndefinedInstruction;
+ else
+ fault = new UndefinedInstruction(false, mnemonic);
+ } else {
destReg.elements[i] = srcReg2.elements[index];
+ }
}
}
'''
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index f319e75aa..b42a1c4b2 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -73,11 +73,10 @@ let {{
swpPreAccCode = '''
if (!((SCTLR)Sctlr).sw) {
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(false, mnemonic);
-#endif
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
}
'''
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 6d84fbf7b..2c86d3d84 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -46,7 +46,6 @@
#include "arch/arm/isa_traits.hh"
#include "arch/arm/utility.hh"
#include "arch/arm/vtophys.hh"
-#include "config/full_system.hh"
#include "sim/serialize.hh"
namespace ArmISA {
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 223ff4c69..528e19acf 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -134,11 +134,6 @@
#include <string>
-#include "config/full_system.hh"
-#if FULL_SYSTEM
-#include "arch/arm/vtophys.hh"
-#endif
-
#include "arch/arm/pagetable.hh"
#include "arch/arm/registers.hh"
#include "arch/arm/remote_gdb.hh"
@@ -157,6 +152,7 @@
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
using namespace std;
@@ -173,28 +169,28 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
bool
RemoteGDB::acc(Addr va, size_t len)
{
-#if FULL_SYSTEM
- Addr last_va;
- va = truncPage(va);
- last_va = roundPage(va + len);
-
- do {
- if (virtvalid(context, va)) {
- return true;
- }
- va += PageBytes;
- } while (va < last_va);
-
- DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
- return true;
-#else
- TlbEntry entry;
- //Check to make sure the first byte is mapped into the processes address
- //space.
- if (context->getProcessPtr()->pTable->lookup(va, entry))
+ if (FullSystem) {
+ Addr last_va;
+ va = truncPage(va);
+ last_va = roundPage(va + len);
+
+ do {
+ if (virtvalid(context, va)) {
+ return true;
+ }
+ va += PageBytes;
+ } while (va < last_va);
+
+ DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
return true;
- return false;
-#endif
+ } else {
+ TlbEntry entry;
+ //Check to make sure the first byte is mapped into the processes address
+ //space.
+ if (context->getProcessPtr()->pTable->lookup(va, entry))
+ return true;
+ return false;
+ }
}
/*
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a03e445cf..6953090d0 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -47,6 +47,8 @@
#include "arch/arm/faults.hh"
#include "arch/arm/pagetable.hh"
+#include "arch/arm/system.hh"
+#include "arch/arm/table_walker.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/utility.hh"
#include "base/inifile.hh"
@@ -58,29 +60,20 @@
#include "debug/TLBVerbose.hh"
#include "mem/page_table.hh"
#include "params/ArmTLB.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
-#if FULL_SYSTEM
-#include "arch/arm/system.hh"
-#include "arch/arm/table_walker.hh"
-#endif
-
using namespace std;
using namespace ArmISA;
TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size)
-#if FULL_SYSTEM
- , tableWalker(p->walker)
-#endif
- , rangeMRU(1), bootUncacheability(false), miscRegValid(false)
+ : BaseTLB(p), size(p->size) , tableWalker(p->walker),
+ rangeMRU(1), bootUncacheability(false), miscRegValid(false)
{
table = new TlbEntry[size];
memset(table, 0, sizeof(TlbEntry) * size);
-#if FULL_SYSTEM
tableWalker->setTlb(this);
-#endif
}
TLB::~TLB()
@@ -404,7 +397,6 @@ TLB::regStats()
accesses = readAccesses + writeAccesses + instAccesses;
}
-#if !FULL_SYSTEM
Fault
TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
Translation *translation, bool &delay, bool timing)
@@ -426,18 +418,18 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
}
}
- Addr paddr;
- Process *p = tc->getProcessPtr();
+ if (!FullSystem) {
+ Addr paddr;
+ Process *p = tc->getProcessPtr();
- if (!p->pTable->translate(vaddr, paddr))
- return Fault(new GenericPageTableFault(vaddr));
- req->setPaddr(paddr);
+ if (!p->pTable->translate(vaddr, paddr))
+ return Fault(new GenericPageTableFault(vaddr));
+ req->setPaddr(paddr);
+ }
return NoFault;
}
-#else // FULL_SYSTEM
-
Fault
TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
{
@@ -578,10 +570,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
}
}
-
- if (!bootUncacheability &&
- ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
- req->setFlags(Request::UNCACHEABLE);
+ if (FullSystem) {
+ if (!bootUncacheability &&
+ ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
+ req->setFlags(Request::UNCACHEABLE);
+ }
switch ( (dacr >> (te->domain * 2)) & 0x3) {
case 0:
@@ -684,18 +677,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
return NoFault;
}
-#endif
-
Fault
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
bool delay = false;
Fault fault;
-#if FULL_SYSTEM
- fault = translateFs(req, tc, mode, NULL, delay, false);
-#else
- fault = translateSe(req, tc, mode, NULL, delay, false);
-#endif
+ if (FullSystem)
+ fault = translateFs(req, tc, mode, NULL, delay, false);
+ else
+ fault = translateSe(req, tc, mode, NULL, delay, false);
assert(!delay);
return fault;
}
@@ -707,11 +697,10 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
assert(translation);
bool delay = false;
Fault fault;
-#if FULL_SYSTEM
- fault = translateFs(req, tc, mode, translation, delay, true);
-#else
- fault = translateSe(req, tc, mode, translation, delay, true);
-#endif
+ if (FullSystem)
+ fault = translateFs(req, tc, mode, translation, delay, true);
+ else
+ fault = translateSe(req, tc, mode, translation, delay, true);
DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
NoFault);
if (!delay)
@@ -724,11 +713,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
Port*
TLB::getPort()
{
-#if FULL_SYSTEM
return tableWalker->getPort("port");
-#else
- return NULL;
-#endif
}
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 3464e42b3..0bf13fe83 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -89,9 +89,7 @@ class TLB : public BaseTLB
uint32_t _attr; // Memory attributes for last accessed TLB entry
-#if FULL_SYSTEM
TableWalker *tableWalker;
-#endif
/** Lookup an entry in the TLB
* @param vpn virtual address
@@ -195,13 +193,10 @@ class TLB : public BaseTLB
return _attr;
}
-#if FULL_SYSTEM
Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
Translation *translation, bool &delay, bool timing);
-#else
Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
Translation *translation, bool &delay, bool timing);
-#endif
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
Fault translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index bbba38d2b..6c2997a27 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -40,15 +40,12 @@
#include "arch/arm/faults.hh"
#include "arch/arm/isa_traits.hh"
+#include "arch/arm/tlb.hh"
#include "arch/arm/utility.hh"
-#include "cpu/thread_context.hh"
-
-#if FULL_SYSTEM
#include "arch/arm/vtophys.hh"
+#include "cpu/thread_context.hh"
#include "mem/vport.hh"
-#endif
-
-#include "arch/arm/tlb.hh"
+#include "sim/full_system.hh"
namespace ArmISA {
@@ -66,49 +63,49 @@ initCPU(ThreadContext *tc, int cpuId)
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
- if (size == (uint16_t)(-1))
- size = ArmISA::MachineBytes;
- if (fp)
- panic("getArgument(): Floating point arguments not implemented\n");
-
- if (number < NumArgumentRegs) {
- // If the argument is 64 bits, it must be in an even regiser number
- // Increment the number here if it isn't even
- if (size == sizeof(uint64_t)) {
- if ((number % 2) != 0)
- number++;
- // Read the two halves of the data
- // number is inc here to get the second half of the 64 bit reg
- uint64_t tmp;
- tmp = tc->readIntReg(number++);
- tmp |= tc->readIntReg(number) << 32;
- return tmp;
+ if (FullSystem) {
+ if (size == (uint16_t)(-1))
+ size = ArmISA::MachineBytes;
+ if (fp)
+ panic("getArgument(): Floating point arguments not implemented\n");
+
+ if (number < NumArgumentRegs) {
+ // If the argument is 64 bits, it must be in an even regiser
+ // number. Increment the number here if it isn't even.
+ if (size == sizeof(uint64_t)) {
+ if ((number % 2) != 0)
+ number++;
+ // Read the two halves of the data. Number is inc here to
+ // get the second half of the 64 bit reg.
+ uint64_t tmp;
+ tmp = tc->readIntReg(number++);
+ tmp |= tc->readIntReg(number) << 32;
+ return tmp;
+ } else {
+ return tc->readIntReg(number);
+ }
} else {
- return tc->readIntReg(number);
- }
- } else {
- Addr sp = tc->readIntReg(StackPointerReg);
- VirtualPort *vp = tc->getVirtPort();
- uint64_t arg;
- if (size == sizeof(uint64_t)) {
- // If the argument is even it must be aligned
- if ((number % 2) != 0)
+ Addr sp = tc->readIntReg(StackPointerReg);
+ VirtualPort *vp = tc->getVirtPort();
+ uint64_t arg;
+ if (size == sizeof(uint64_t)) {
+ // If the argument is even it must be aligned
+ if ((number % 2) != 0)
+ number++;
+ arg = vp->read<uint64_t>(sp +
+ (number-NumArgumentRegs) * sizeof(uint32_t));
+ // since two 32 bit args == 1 64 bit arg, increment number
number++;
- arg = vp->read<uint64_t>(sp +
- (number-NumArgumentRegs) * sizeof(uint32_t));
- // since two 32 bit args == 1 64 bit arg, increment number
- number++;
- } else {
- arg = vp->read<uint32_t>(sp +
- (number-NumArgumentRegs) * sizeof(uint32_t));
+ } else {
+ arg = vp->read<uint32_t>(sp +
+ (number-NumArgumentRegs) * sizeof(uint32_t));
+ }
+ return arg;
}
- return arg;
+ } else {
+ panic("getArgument() only implemented for full system mode.\n");
+ M5_DUMMY_RETURN
}
-#else
- panic("getArgument() only implemented for FULL_SYSTEM\n");
- M5_DUMMY_RETURN
-#endif
}
void
diff --git a/src/arch/mips/BISystem.py b/src/arch/mips/BISystem.py
index a6e4091f2..d5e02485e 100755
--- a/src/arch/mips/BISystem.py
+++ b/src/arch/mips/BISystem.py
@@ -32,10 +32,9 @@ from m5.defines import buildEnv
from System import *
-if buildEnv['FULL_SYSTEM']:
- class BareIronMipsSystem(MipsSystem):
- type = 'BareIronMipsSystem'
- system_type = 34
- system_rev = 1 << 10
- hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class BareIronMipsSystem(MipsSystem):
+ type = 'BareIronMipsSystem'
+ system_type = 34
+ system_rev = 1 << 10
+ hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index fc4f1efa3..4a0851eba 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -43,16 +43,18 @@ class MipsSystem(System):
system_rev = Param.UInt64("Revision of system we are emulating")
load_addr_mask = 0xffffffffff
-if buildEnv['FULL_SYSTEM']:
- class LinuxMipsSystem(MipsSystem):
- type = 'LinuxMipsSystem'
- system_type = 34
- system_rev = 1 << 10
-
- class BareIronMipsSystem(MipsSystem):
- type = 'BareIronMipsSystem'
- bare_iron = True
- system_type = 34
- system_rev = 1 << 10
- hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class LinuxMipsSystem(MipsSystem):
+ type = 'LinuxMipsSystem'
+ system_type = 34
+ system_rev = 1 << 10
+
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ "boot processor frequency")
+
+class BareIronMipsSystem(MipsSystem):
+ type = 'BareIronMipsSystem'
+ bare_iron = True
+ system_type = 34
+ system_rev = 1 << 10
+ hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 9fc2b71ff..7e2d4b806 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -33,32 +33,29 @@
Import('*')
if env['TARGET_ISA'] == 'mips':
+ Source('bare_iron/system.cc')
+ Source('dsp.cc')
Source('faults.cc')
+ Source('idle_event.cc')
+ Source('interrupts.cc')
Source('isa.cc')
- Source('tlb.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
Source('pagetable.cc')
- Source('utility.cc')
- Source('dsp.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
+ Source('tlb.cc')
+ Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('MipsInterrupts.py')
+ SimObject('MipsSystem.py')
SimObject('MipsTLB.py')
- DebugFlag('MipsPRA')
- if env['FULL_SYSTEM']:
- SimObject('MipsSystem.py')
- SimObject('MipsInterrupts.py')
- Source('idle_event.cc')
- Source('mips_core_specific.cc')
- Source('vtophys.cc')
- Source('system.cc')
- Source('stacktrace.cc')
- Source('linux/system.cc')
- Source('interrupts.cc')
- Source('bare_iron/system.cc')
- else:
- Source('process.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
+ DebugFlag('MipsPRA')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index 49698eec6..3f6c6866e 100755
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -32,7 +32,6 @@
#include "arch/mips/isa_traits.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "sim/serialize.hh"
diff --git a/src/arch/mips/dsp.hh b/src/arch/mips/dsp.hh
index f13431714..0e9424f38 100755
--- a/src/arch/mips/dsp.hh
+++ b/src/arch/mips/dsp.hh
@@ -35,7 +35,6 @@
#include "arch/mips/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
class ThreadContext;
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 9ec93f3fe..524efa178 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -37,11 +37,8 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
-
-#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
namespace MipsISA
{
@@ -134,7 +131,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
void
MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
setExceptionState(tc, code());
tc->pcState(vect(tc));
@@ -146,7 +143,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
void
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "%s encountered.\n", name());
/* All reset activity must be invoked from here */
Addr handler = vect(tc);
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 89b6924c6..bce828ec1 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -38,6 +38,7 @@
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
namespace MipsISA
{
@@ -163,7 +164,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
- if (FULL_SYSTEM) {
+ if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID;
tc->setMiscReg(MISCREG_CAUSE, cause);
@@ -197,7 +198,7 @@ class AddressFault : public MipsFault<T>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
- if (FULL_SYSTEM)
+ if (FullSystem)
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
}
};
@@ -249,7 +250,7 @@ class TlbFault : public AddressFault<T>
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
tc->pcState(this->vect(tc));
setTlbExceptionState(tc, this->code());
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 096aa628f..f4221ab2c 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -36,6 +36,7 @@
#include "arch/mips/pra_constants.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
namespace MipsISA
{
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 179e409dd..193f050de 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
- 0x4: decode FULL_SYSTEM {
+ 0x4: decode FullSystem {
0: syscall_se({{ xc->syscall(R2); }},
IsSerializeAfter, IsNonSpeculative);
default: syscall({{ fault = new SystemCallFault(); }});
@@ -212,7 +212,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: add({{
IntReg result;
Rd = result = Rs + Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, Rt)) {
fault = new IntegerOverflowFault();
}
@@ -221,7 +221,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: sub({{
IntReg result;
Rd = result = Rs - Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, ~Rt)) {
fault = new IntegerOverflowFault();
}
@@ -325,7 +325,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: addi({{
IntReg result;
Rt = result = Rs + imm;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, imm)) {
fault = new IntegerOverflowFault();
}
@@ -2431,7 +2431,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
0x3: decode OP default FailUnimpl::rdhwr() {
- 0x0: decode FULL_SYSTEM {
+ 0x0: decode FullSystem {
0: decode RD {
29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
}
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 7e90ed3e5..2d6748c05 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -128,7 +128,7 @@ def template ControlTLBExecute {{
%(op_decl)s;
%(op_rd)s;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (isCoprocessor0Enabled(xc)) {
if(isMMUTLB(xc)){
%(code)s;
@@ -176,7 +176,7 @@ output exec {{
bool
isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
- if (!FULL_SYSTEM)
+ if (!FullSystem)
return true;
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -198,7 +198,7 @@ output exec {{
bool inline
isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
@@ -215,7 +215,7 @@ output exec {{
isMMUTLB(%(CPU_exec_context)s *xc)
{
MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
- return FULL_SYSTEM && (Config & 0x380) == 0x80;
+ return FullSystem && (Config & 0x380) == 0x80;
}
}};
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 2eeefe806..b288b7b20 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -143,7 +143,7 @@ output exec {{
bool
isDspEnabled(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
}
}};
@@ -151,7 +151,7 @@ output exec {{
bool
isDspPresent(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
}
}};
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index f99d2327e..63823f404 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -174,7 +174,7 @@ def template FloatingPointExecute {{
//When is the right time to reset cause bits?
//start of every instruction or every cycle?
- if (FULL_SYSTEM)
+ if (FullSystem)
fpResetCauseBits(xc);
%(op_decl)s;
%(op_rd)s;
@@ -191,7 +191,7 @@ def template FloatingPointExecute {{
//Check for IEEE 754 FP Exceptions
//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
bool invalid_op = false;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
invalid_op =
fpInvalidOp((FPOp*)this, xc, Fd, traceData);
}
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 65b4425af..d567a113f 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -193,7 +193,7 @@ output exec {{
CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 0))
return new CoprocessorUnusableFault(0);
else
@@ -210,7 +210,7 @@ output exec {{
CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 1))
return new CoprocessorUnusableFault(1);
else
@@ -227,7 +227,7 @@ output exec {{
CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 2))
return new CoprocessorUnusableFault(2);
else
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 4ce03b1c2..d2e9c797e 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -60,6 +60,7 @@ output decoder {{
#include "base/cprintf.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
+#include "sim/full_system.hh"
#if defined(linux)
#include <fenv.h>
#endif
@@ -92,6 +93,7 @@ output exec {{
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 5cef45523..f2a748da9 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -34,10 +34,8 @@
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
-#include "arch/mips/mips_core_specific.hh"
#include "arch/mips/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace LittleEndianGuest {}
diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc
index 67e21574e..30e0f95e9 100644
--- a/src/arch/mips/linux/system.cc
+++ b/src/arch/mips/linux/system.cc
@@ -47,6 +47,7 @@
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/Thread.hh"
#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
@@ -76,7 +77,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
* Since we aren't using a bootloader, we have to copy the
* kernel arguments directly into the kernel's memory.
*/
- virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
+ virtPort->writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
params()->boot_osflags.length()+1);
/**
@@ -85,7 +86,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
* calculated it by using the PIT, RTC, etc.
*/
if (kernelSymtab->findAddress("est_cycle_freq", addr))
- virtPort.write(addr, (uint64_t)(SimClock::Frequency /
+ virtPort->write(addr, (uint64_t)(SimClock::Frequency /
p->boot_cpu_frequency));
/**
@@ -95,7 +96,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
* 255 ASNs.
*/
if (kernelSymtab->findAddress("dp264_mv", addr))
- virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+ virtPort->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
else
panic("could not find dp264_mv\n");
@@ -153,15 +154,7 @@ LinuxMipsSystem::~LinuxMipsSystem()
void
LinuxMipsSystem::setDelayLoop(ThreadContext *tc)
{
- Addr addr = 0;
- if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
- Tick cpuFreq = tc->getCpuPtr()->frequency();
- Tick intrFreq = platform->intrFrequency();
- VirtualPort *vp;
-
- vp = tc->getVirtPort();
- vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
- }
+ panic("setDelayLoop not implemented.\n");
}
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index cd269f1af..8678eb7e4 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -34,34 +34,14 @@
#ifndef __ARCH_MIPS_PAGETABLE_H__
#define __ARCH_MIPS_PAGETABLE_H__
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
namespace MipsISA {
struct VAddr
{
- static const int ImplBits = 43;
- static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
- static const Addr UnImplMask = ~ImplMask;
-
- VAddr(Addr a) : addr(a) {}
- Addr addr;
- operator Addr() const { return addr; }
- const VAddr &operator=(Addr a) { addr = a; return *this; }
-
- Addr vpn() const { return (addr & ImplMask) >> PageShift; }
- Addr page() const { return addr & Page_Mask; }
- Addr offset() const { return addr & PageOffset; }
-
- Addr level3() const
- { return MipsISA::PteAddr(addr >> PageShift); }
- Addr level2() const
- { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
- Addr level1() const
- { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
// ITB/DTB page table entry
@@ -98,6 +78,33 @@ struct PTE
void unserialize(Checkpoint *cp, const std::string &section);
};
+// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
+struct TlbEntry
+{
+ Addr _pageStart;
+ TlbEntry() {}
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+
+ Addr pageStart()
+ {
+ return _pageStart;
+ }
+
+ void
+ updateVaddr(Addr new_vaddr) {}
+
+ void serialize(std::ostream &os)
+ {
+ SERIALIZE_SCALAR(_pageStart);
+ }
+
+ void unserialize(Checkpoint *cp, const std::string &section)
+ {
+ UNSERIALIZE_SCALAR(_pageStart);
+ }
+
+};
+
};
#endif // __ARCH_MIPS_PAGETABLE_H__
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 1fd157758..656cb8cbb 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -137,12 +137,12 @@
#include "arch/mips/remote_gdb.hh"
#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
#include "cpu/decode.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "mem/page_table.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace MipsISA;
@@ -158,13 +158,13 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
bool
RemoteGDB::acc(Addr va, size_t len)
{
-#if FULL_SYSTEM
- panic("acc not implemented for MIPS FS!");
-#endif
TlbEntry entry;
//Check to make sure the first byte is mapped into the processes address
//space.
- return context->getProcessPtr()->pTable->lookup(va, entry);
+ if (FullSystem)
+ panic("acc not implemented for MIPS FS!");
+ else
+ return context->getProcessPtr()->pTable->lookup(va, entry);
}
/*
diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc
index f3bcb5e68..50f6e1fb0 100644
--- a/src/arch/mips/stacktrace.cc
+++ b/src/arch/mips/stacktrace.cc
@@ -37,6 +37,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "mem/vport.hh"
#include "sim/system.hh"
using namespace std;
diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index c1735b740..d367acd64 100755
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -38,6 +38,7 @@
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "mem/physical.hh"
+#include "mem/vport.hh"
#include "params/MipsSystem.hh"
#include "sim/byteswap.hh"
@@ -45,8 +46,6 @@ using namespace LittleEndianGuest;
MipsSystem::MipsSystem(Params *p) : System(p)
{
-
-#if FULL_SYSTEM
if (p->bare_iron == true) {
hexFile = new HexFile(params()->hex_file_name);
if (!hexFile->loadSections(functionalPort))
@@ -108,14 +107,12 @@ MipsSystem::MipsSystem(Params *p) : System(p)
} else {
panic("could not find hwrpb\n");
}
-#endif
}
MipsSystem::~MipsSystem()
{
}
-#if FULL_SYSTEM
Addr
MipsSystem::fixFuncEventAddr(Addr addr)
{
@@ -126,8 +123,6 @@ void
MipsSystem::setMipsAccess(Addr access)
{}
-#endif
-
bool
MipsSystem::breakpoint()
{
diff --git a/src/arch/mips/system.hh b/src/arch/mips/system.hh
index 128f36581..fcaceadcd 100755
--- a/src/arch/mips/system.hh
+++ b/src/arch/mips/system.hh
@@ -66,7 +66,6 @@ class MipsSystem : public System
*/
void setMipsAccess(Addr access);
-#if FULL_SYSTEM
/** console symbol table */
SymbolTable *consoleSymtab;
@@ -75,7 +74,6 @@ class MipsSystem : public System
/** Used by some Bare Iron Configurations */
HexFile *hexFile;
-#endif
#ifndef NDEBUG
/** Event to halt the simulator if the console calls panic() */
@@ -85,9 +83,7 @@ class MipsSystem : public System
protected:
const Params *params() const { return (const Params *)_params; }
-
-#if FULL_SYSTEM
- /** Add a function-based event to the console code. */
+ /** Add a function-based event to the console code. */
template <class T>
T *
addConsoleFuncEvent(const char *lbl)
@@ -96,7 +92,6 @@ class MipsSystem : public System
}
virtual Addr fixFuncEventAddr(Addr addr);
-#endif
};
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 57d8849e1..057fb5e76 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -293,182 +293,45 @@ TLB::regStats()
Fault
TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
-#if !FULL_SYSTEM
- Process * p = tc->getProcessPtr();
+ if (!FullSystem) {
+ Process * p = tc->getProcessPtr();
- Fault fault = p->pTable->translate(req);
- if (fault != NoFault)
- return fault;
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
- return NoFault;
-#else
- Addr vaddr = req->getVaddr();
-
- bool misaligned = (req->getSize() - 1) & vaddr;
-
- if (IsKSeg0(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
- if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
- misaligned) {
- return new AddressErrorFault(vaddr, false);
- }
- } else if(IsKSeg1(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
+ return NoFault;
} else {
- /*
- * This is an optimization - smallPages is updated every time a TLB
- * operation is performed. That way, we don't need to look at
- * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
- */
- Addr VPN;
- if (smallPages == 1) {
- VPN = (vaddr >> 11);
- } else {
- VPN = ((vaddr >> 11) & 0xFFFFFFFC);
- }
- uint8_t Asid = req->getAsid();
- if (misaligned) {
- // Unaligned address!
- return new AddressErrorFault(vaddr, false);
- }
- PTE *pte = lookup(VPN,Asid);
- if (pte != NULL) {
- // Ok, found something
- /* Check for valid bits */
- int EvenOdd;
- bool Valid;
- if ((((vaddr) >> pte->AddrShiftAmount) & 1) == 0) {
- // Check even bits
- Valid = pte->V0;
- EvenOdd = 0;
- } else {
- // Check odd bits
- Valid = pte->V1;
- EvenOdd = 1;
- }
-
- if (Valid == false) {
- return new InvalidFault(Asid, vaddr, vpn, false);
- } else {
- // Ok, this is really a match, set paddr
- Addr PAddr;
- if (EvenOdd == 0) {
- PAddr = pte->PFN0;
- } else {
- PAddr = pte->PFN1;
- }
- PAddr >>= (pte->AddrShiftAmount - 12);
- PAddr <<= pte->AddrShiftAmount;
- PAddr |= (vaddr & pte->OffsetMask);
- req->setPaddr(PAddr);
- }
- } else {
- // Didn't find any match, return a TLB Refill Exception
- return new RefillFault(Asid, vaddr, vpn, false);
- }
+ panic("translateInst not implemented in MIPS.\n");
}
- return checkCacheability(req);
-#endif
}
Fault
TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
{
-#if !FULL_SYSTEM
- //@TODO: This should actually use TLB instead of going directly
- // to the page table in syscall mode.
- /**
- * Check for alignment faults
- */
- if (req->getVaddr() & (req->getSize() - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
- req->getSize());
- return new AddressErrorFault(req->getVaddr(), write);
- }
-
-
- Process * p = tc->getProcessPtr();
+ if (!FullSystem) {
+ //@TODO: This should actually use TLB instead of going directly
+ // to the page table in syscall mode.
+ /**
+ * Check for alignment faults
+ */
+ if (req->getVaddr() & (req->getSize() - 1)) {
+ DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
+ req->getSize());
+ return new AddressErrorFault(req->getVaddr(), write);
+ }
- Fault fault = p->pTable->translate(req);
- if (fault != NoFault)
- return fault;
- return NoFault;
-#else
- Addr vaddr = req->getVaddr();
+ Process * p = tc->getProcessPtr();
- bool misaligned = (req->getSize() - 1) & vaddr;
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
- if (IsKSeg0(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
- if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
- misaligned) {
- return new AddressErrorFault(vaddr, true);
- }
- } else if(IsKSeg1(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
+ return NoFault;
} else {
- /*
- * This is an optimization - smallPages is updated every time a TLB
- * operation is performed. That way, we don't need to look at
- * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
- */
- Addr VPN = (vaddr >> 11) & 0xFFFFFFFC;
- if (smallPages == 1) {
- VPN = vaddr >> 11;
- }
- uint8_t Asid = req->getAsid();
- PTE *pte = lookup(VPN, Asid);
- if (misaligned) {
- return new AddressErrorFault(vaddr, true);
- }
- if (pte != NULL) {
- // Ok, found something
- /* Check for valid bits */
- int EvenOdd;
- bool Valid;
- bool Dirty;
- if ((((vaddr >> pte->AddrShiftAmount) & 1)) == 0) {
- // Check even bits
- Valid = pte->V0;
- Dirty = pte->D0;
- EvenOdd = 0;
- } else {
- // Check odd bits
- Valid = pte->V1;
- Dirty = pte->D1;
- EvenOdd = 1;
- }
-
- if (Valid == false) {
- return new InvalidFault(Asid, vaddr, VPN, true);
- } else {
- // Ok, this is really a match, set paddr
- if (!Dirty) {
- return new TlbModifiedFault(Asid, vaddr, VPN);
- }
- Addr PAddr;
- if (EvenOdd == 0) {
- PAddr = pte->PFN0;
- } else {
- PAddr = pte->PFN1;
- }
- PAddr >>= (pte->AddrShiftAmount - 12);
- PAddr <<= pte->AddrShiftAmount;
- PAddr |= (vaddr & pte->OffsetMask);
- req->setPaddr(PAddr);
- }
- } else {
- // Didn't find any match, return a TLB Refill Exception
- return new RefillFault(Asid, vaddr, VPN, true);
- }
+ panic("translateData not implemented in MIPS.\n");
}
- return checkCacheability(req);
-#endif
}
Fault
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 4b1456862..834431536 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -55,33 +55,6 @@ class ThreadContext;
simply create an ITLB and DTLB that will point to the real TLB */
namespace MipsISA {
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
- Addr _pageStart;
- TlbEntry() {}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
- Addr pageStart()
- {
- return _pageStart;
- }
-
- void
- updateVaddr(Addr new_vaddr) {}
-
- void serialize(std::ostream &os)
- {
- SERIALIZE_SCALAR(_pageStart);
- }
-
- void unserialize(Checkpoint *cp, const std::string &section)
- {
- UNSERIALIZE_SCALAR(_pageStart);
- }
-
-};
-
class TLB : public BaseTLB
{
protected:
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 37f71416f..1f3b19c7b 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -34,16 +34,13 @@
#include "arch/mips/utility.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/serialize.hh"
-#if FULL_SYSTEM
#include "arch/mips/registers.hh"
#include "arch/mips/vtophys.hh"
#include "mem/vport.hh"
-#endif
using namespace MipsISA;
@@ -54,23 +51,8 @@ namespace MipsISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
- if (number < 4) {
- if (fp)
- return tc->readFloatRegBits(FirstArgumentReg + number);
- else
- return tc->readIntReg(FirstArgumentReg + number);
- } else {
- Addr sp = tc->readIntReg(StackPointerReg);
- VirtualPort *vp = tc->getVirtPort();
- uint64_t arg = vp->read<uint64_t>(sp +
- (number - 4) * sizeof(uint64_t));
- return arg;
- }
-#else
- panic("getArgument() is Full system only\n");
+ panic("getArgument() not implemented\n");
M5_DUMMY_RETURN
-#endif
}
uint64_t
@@ -254,6 +236,10 @@ startupCPU(ThreadContext *tc, int cpuId)
}
void
+initCPU(ThreadContext *tc, int cpuId)
+{}
+
+void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
panic("Copy Regs Not Implemented Yet\n");
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index a2995b098..876066203 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -37,7 +37,6 @@
#include "arch/mips/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
@@ -108,6 +107,7 @@ RoundPage(Addr addr)
// CPU Utility
//
void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index 08e1a1e1c..c6a317df8 100755
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -37,6 +37,7 @@
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/VtoPhys.hh"
#include "mem/vport.hh"
using namespace std;
@@ -45,25 +46,13 @@ using namespace MipsISA;
Addr
MipsISA::vtophys(Addr vaddr)
{
- Addr paddr = 0;
- if (MipsISA::IsUSeg(vaddr))
- DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- else if (MipsISA::IsKSeg0(vaddr))
- paddr = MipsISA::KSeg02Phys(vaddr);
- else if(MipsISA::IsKSeg1(vaddr))
- paddr = MipsISA::KSeg12Phys(vaddr);
- else
- panic("vtophys: ptbr is not set on "
- "virtual lookup for vaddr %#x", vaddr);
-
- DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
- return paddr;
+ fatal("VTOPHYS: Unimplemented on MIPS\n");
+ return 0;
}
Addr
MipsISA::vtophys(ThreadContext *tc, Addr addr)
{
- fatal("VTOPHYS: Unimplemented on MIPS\n");
+ fatal("VTOPHYS: Unimplemented on MIPS\n");
}
diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 5ecc30b1f..37a7378a8 100644
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -41,24 +41,6 @@ class ThreadContext;
class FunctionalPort;
namespace MipsISA {
- inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
- // User Virtual
- inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
-
- inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
-
- inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
-
- inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
-
- inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
-
- inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
-
- inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
-
-
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
diff --git a/src/arch/power/PowerInterrupts.py b/src/arch/power/PowerInterrupts.py
new file mode 100644
index 000000000..82d614077
--- /dev/null
+++ b/src/arch/power/PowerInterrupts.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2011 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class PowerInterrupts(SimObject):
+ type = 'PowerInterrupts'
+ cxx_class = 'PowerISA::Interrupts'
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index f96f12757..7f893ca37 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -40,17 +40,20 @@ if env['TARGET_ISA'] == 'power':
Source('insts/floating.cc')
Source('insts/condition.cc')
Source('insts/static_inst.cc')
+ Source('interrupts.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
Source('pagetable.cc')
+ Source('process.cc')
+ Source('stacktrace.cc')
Source('tlb.cc')
Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('PowerInterrupts.py')
SimObject('PowerTLB.py')
- DebugFlag('Power')
- if not env['FULL_SYSTEM']:
- Source('process.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
+ DebugFlag('Power')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/power/interrupts.cc
index bd66e049f..c9ef36824 100644
--- a/src/arch/mips/mips_core_specific.hh
+++ b/src/arch/power/interrupts.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2011 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,18 +25,13 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Jaidev Patwardhan
+ * Authors: Gabe Black
*/
-#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
-#define __ARCH_MIPS_CORE_SPECIFIC_HH__
+#include "arch/power/interrupts.hh"
-#include "arch/mips/isa_traits.hh"
-
-class ThreadContext;
-
-namespace MipsISA {
- void initCPU(ThreadContext *tc, int cpuId);
-};
-
-#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__
+PowerISA::Interrupts *
+PowerInterruptsParams::create()
+{
+ return new PowerISA::Interrupts(this);
+}
diff --git a/src/arch/power/interrupts.hh b/src/arch/power/interrupts.hh
new file mode 100644
index 000000000..9c11c8e8a
--- /dev/null
+++ b/src/arch/power/interrupts.hh
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_INTERRUPT_HH__
+#define __ARCH_POWER_INTERRUPT_HH__
+
+#include "base/misc.hh"
+#include "params/PowerInterrupts.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+namespace PowerISA {
+
+class Interrupts : public SimObject
+{
+ private:
+ BaseCPU * cpu;
+
+ public:
+ typedef PowerInterruptsParams Params;
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
+ Interrupts(Params * p) : SimObject(p), cpu(NULL)
+ {}
+
+ void
+ setCPU(BaseCPU * _cpu)
+ {
+ cpu = _cpu;
+ }
+
+ void
+ post(int int_num, int index)
+ {
+ panic("Interrupts::post not implemented.\n");
+ }
+
+ void
+ clear(int int_num, int index)
+ {
+ panic("Interrupts::clear not implemented.\n");
+ }
+
+ void
+ clearAll()
+ {
+ panic("Interrupts::clearAll not implemented.\n");
+ }
+
+ bool
+ checkInterrupts(ThreadContext *tc) const
+ {
+ panic("Interrupts::checkInterrupts not implemented.\n");
+ }
+
+ Fault
+ getInterrupt(ThreadContext *tc)
+ {
+ panic("Interrupts::getInterrupt not implemented.\n");
+ }
+
+ void
+ updateIntrInfo(ThreadContext *tc)
+ {
+ panic("Interrupts::updateIntrInfo not implemented.\n");
+ }
+};
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_INTERRUPT_HH__
+
diff --git a/src/arch/power/kernel_stats.hh b/src/arch/power/kernel_stats.hh
new file mode 100644
index 000000000..b4d9a69b6
--- /dev/null
+++ b/src/arch/power/kernel_stats.hh
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_KERNEL_STATS_HH__
+#define __ARCH_POWER_KERNEL_STATS_HH__
+
+#include "kern/kernel_stats.hh"
+
+namespace PowerISA {
+namespace Kernel {
+
+enum cpu_mode { hypervisor, kernel, user, idle, cpu_mode_num };
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
+{
+ public:
+ Statistics(System *system) : ::Kernel::Statistics(system)
+ {}
+};
+
+} // namespace PowerISA::Kernel
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_KERNEL_STATS_HH__
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index a5f18eba9..3097aa526 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -41,7 +41,6 @@
#include "arch/power/isa_traits.hh"
#include "arch/power/utility.hh"
#include "arch/power/vtophys.hh"
-#include "config/full_system.hh"
namespace PowerISA {
diff --git a/src/arch/power/stacktrace.cc b/src/arch/power/stacktrace.cc
new file mode 100644
index 000000000..5fcb6342c
--- /dev/null
+++ b/src/arch/power/stacktrace.cc
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <string>
+
+#include "arch/power/stacktrace.hh"
+#include "base/trace.hh"
+
+using namespace std;
+
+namespace PowerISA {
+
+ProcessInfo::ProcessInfo(ThreadContext *_tc)
+ : tc(_tc)
+{
+ panic("ProcessInfo constructor not implemented.\n");
+}
+
+Addr
+ProcessInfo::task(Addr ksp) const
+{
+ panic("ProcessInfo::task not implemented.\n");
+ return 0;
+}
+
+int
+ProcessInfo::pid(Addr ksp) const
+{
+ panic("ProcessInfo::pid not implemented.\n");
+ return 0;
+}
+
+string
+ProcessInfo::name(Addr ksp) const
+{
+ panic("ProcessInfo::name not implemented.\n");
+ return "";
+}
+
+StackTrace::StackTrace()
+ : tc(0), stack(64)
+{
+ panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+ : tc(0), stack(64)
+{
+ panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::~StackTrace()
+{
+ panic("StackTrace destructor not implemented.\n");
+}
+
+void
+StackTrace::trace(ThreadContext *_tc, bool is_call)
+{
+ panic("StackTrace::trace not implemented.\n");
+}
+
+bool
+StackTrace::isEntry(Addr addr)
+{
+ panic("StackTrace::isEntry not implemented.\n");
+ return false;
+}
+
+bool
+StackTrace::decodeStack(MachInst inst, int &disp)
+{
+ panic("StackTrace::decodeStack not implemented.\n");
+ return false;
+}
+
+bool
+StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+{
+ panic("StackTrace::decodeSave not implemented.\n");
+ return true;
+}
+
+/*
+ * Decode the function prologue for the function we're in, and note
+ * which registers are stored where, and how large the stack frame is.
+ */
+bool
+StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, int &size,
+ Addr &ra)
+{
+ panic("StackTrace::decodePrologue not implemented.\n");
+ return true;
+}
+
+#if TRACING_ON
+void
+StackTrace::dump()
+{
+ panic("StackTrace::dump not implemented.\n");
+}
+#endif
+
+} // namespace PowerISA
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 0b3edd5a2..2148e875a 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -50,6 +50,7 @@
#include "debug/TLB.hh"
#include "mem/page_table.hh"
#include "params/PowerTLB.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
using namespace std;
@@ -308,14 +309,14 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
Fault
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
-#if !FULL_SYSTEM
- if (mode == Execute)
- return translateInst(req, tc);
- else
- return translateData(req, tc, mode == Write);
-#else
- fatal("translate atomic not yet implemented\n");
-#endif
+ if (FullSystem) {
+ fatal("translate atomic not yet implemented in full system mode.\n");
+ } else {
+ if (mode == Execute)
+ return translateInst(req, tc);
+ else
+ return translateData(req, tc, mode == Write);
+ }
}
void
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index b02ccda08..e3fa246fc 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -55,11 +55,24 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
dest->pcState(src->pcState());
}
+uint64_t
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
+{
+ panic("getArgument not implemented for POWER.\n");
+ return 0;
+}
+
void
skipFunction(ThreadContext *tc)
{
panic("Not Implemented for POWER");
}
+void
+initCPU(ThreadContext *tc, int cpuId)
+{
+ panic("initCPU not implemented for POWER.\n");
+}
+
} // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 349054774..c3868c189 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -78,6 +78,8 @@ advancePC(PCState &pc, const StaticInstPtr inst)
pc.advance();
}
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
static inline bool
inUserMode(ThreadContext *tc)
{
@@ -90,6 +92,8 @@ getExecutingAsid(ThreadContext *tc)
return 0;
}
+void initCPU(ThreadContext *, int cpuId);
+
} // namespace PowerISA
diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/power/vtophys.cc
index 31d47c842..597f41b2f 100755
--- a/src/arch/mips/mips_core_specific.cc
+++ b/src/arch/power/vtophys.cc
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2002, 2005 The Regents of The University of Michigan
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,22 +26,24 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Nathan Binkert
- * Steve Reinhardt
+ * Authors: Ali Saidi
+ * Nathan Binkert
+ * Jaidev Patwardhan
*/
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
+#include "arch/power/vtophys.hh"
-#if FULL_SYSTEM
+using namespace std;
-////////////////////////////////////////////////////////////////////////
-//
-// Machine dependent functions
-//
-void
-MipsISA::initCPU(ThreadContext *tc, int cpuId)
-{}
+Addr
+PowerISA::vtophys(Addr vaddr)
+{
+ fatal("VTOPHYS: Unimplemented on POWER\n");
+}
+
+Addr
+PowerISA::vtophys(ThreadContext *tc, Addr addr)
+{
+ fatal("VTOPHYS: Unimplemented on POWER\n");
+}
-#endif // FULL_SYSTEM || BARE_IRON
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index 7371f38a6..a2582b296 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -44,6 +44,9 @@ class FunctionalPort;
namespace PowerISA {
+Addr vtophys(Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
inline Addr
PteAddr(Addr a)
{
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index cc13d56af..75a3590e7 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -34,37 +34,31 @@ Import('*')
if env['TARGET_ISA'] == 'sparc':
Source('asi.cc')
Source('faults.cc')
+ Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/syscalls.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
+ Source('solaris/process.cc')
+ Source('solaris/solaris.cc')
+ Source('system.cc')
Source('tlb.cc')
+ Source('ua2005.cc')
Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('SparcInterrupts.py')
SimObject('SparcNativeTrace.py')
-
+ SimObject('SparcSystem.py')
SimObject('SparcTLB.py')
+
DebugFlag('Sparc', "Generic SPARC ISA stuff")
DebugFlag('RegisterWindows', "Register window manipulation")
- if env['FULL_SYSTEM']:
- SimObject('SparcSystem.py')
- SimObject('SparcInterrupts.py')
-
- Source('interrupts.cc')
- Source('system.cc')
- Source('ua2005.cc')
- Source('vtophys.cc')
- else:
- Source('process.cc')
-
- Source('linux/linux.cc')
- Source('linux/process.cc')
- Source('linux/syscalls.cc')
-
- Source('solaris/process.cc')
- Source('solaris/solaris.cc')
-
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
# Only non-header files need to be compiled.
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 01d57e627..a737b328d 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -33,17 +33,16 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/process.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
+#include "sim/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#if !FULL_SYSTEM
-#include "arch/sparc/process.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
using namespace std;
@@ -494,12 +493,13 @@ getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
NPC = PC + sizeof(MachInst);
}
-#if FULL_SYSTEM
-
void
SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
+
countStat()++;
// We can refer to this to see what the trap level -was-, but something
@@ -619,94 +619,110 @@ PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
*/
}
-#else // !FULL_SYSTEM
-
void
FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- panic("Tried to execute unmapped address %#x.\n", vaddr);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
} else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
- p->M5_pid /*context id*/, false, entry.pte);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ panic("Tried to execute unmapped address %#x.\n", vaddr);
+ } else {
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+ p->M5_pid /*context id*/, false, entry.pte);
+ }
}
}
void
FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, entry);
- }
- if (!success) {
- panic("Tried to access unmapped address %#x.\n", vaddr);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
} else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
- p->M5_pid /*context id*/, false, entry.pte);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ if (p->fixupStackFault(vaddr))
+ success = p->pTable->lookup(vaddr, entry);
+ }
+ if (!success) {
+ panic("Tried to access unmapped address %#x.\n", vaddr);
+ } else {
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+ p->M5_pid /*context id*/, false, entry.pte);
+ }
}
}
void
SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- doNormalFault(tc, trapType(), false);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
+ } else {
+ doNormalFault(tc, trapType(), false);
- Process *p = tc->getProcessPtr();
+ Process *p = tc->getProcessPtr();
- //XXX This will only work in faults from a SparcLiveProcess
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ //XXX This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
- // Then adjust the PC and NPC
- tc->pcState(lp->readSpillStart());
+ // Then adjust the PC and NPC
+ tc->pcState(lp->readSpillStart());
+ }
}
void
FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- doNormalFault(tc, trapType(), false);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
+ } else {
+ doNormalFault(tc, trapType(), false);
- Process *p = tc->getProcessPtr();
+ Process *p = tc->getProcessPtr();
- //XXX This will only work in faults from a SparcLiveProcess
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ //XXX This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
- // Then adjust the PC and NPC
- tc->pcState(lp->readFillStart());
+ // Then adjust the PC and NPC
+ tc->pcState(lp->readFillStart());
+ }
}
void
TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // In SE, this mechanism is how the process requests a service from the
- // operating system. We'll get the process object from the thread context
- // and let it service the request.
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
+ } else {
+ // In SE, this mechanism is how the process requests a service from
+ // the operating system. We'll get the process object from the thread
+ // context and let it service the request.
- Process *p = tc->getProcessPtr();
+ Process *p = tc->getProcessPtr();
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
- lp->handleTrap(_n, tc);
+ lp->handleTrap(_n, tc);
- // We need to explicitly advance the pc, since that's not done for us
- // on a faulting instruction
- PCState pc = tc->pcState();
- pc.advance();
- tc->pcState(pc);
+ // We need to explicitly advance the pc, since that's not done for us
+ // on a faulting instruction
+ PCState pc = tc->pcState();
+ pc.advance();
+ tc->pcState(pc);
+ }
}
-#endif
-
} // namespace SparcISA
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 88c269d66..148983f4f 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -32,7 +32,6 @@
#ifndef __SPARC_FAULTS_HH__
#define __SPARC_FAULTS_HH__
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "sim/faults.hh"
@@ -66,10 +65,8 @@ class SparcFaultBase : public FaultBase
const PrivilegeLevel nextPrivilegeLevel[NumLevels];
FaultStat count;
};
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
virtual FaultStat & countStat() = 0;
@@ -96,10 +93,8 @@ class SparcFault : public SparcFaultBase
class PowerOnReset : public SparcFault<PowerOnReset>
{
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -204,28 +199,28 @@ class VAWatchpoint : public SparcFault<VAWatchpoint> {};
class FastInstructionAccessMMUMiss :
public SparcFault<FastInstructionAccessMMUMiss>
{
-#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
{}
+ FastInstructionAccessMMUMiss() : vaddr(0)
+ {}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
{
-#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
{}
+ FastDataAccessMMUMiss() : vaddr(0)
+ {}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
@@ -243,10 +238,8 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
public:
SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
// These need to be handled specially to enable spill traps in SE
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class SpillNOther : public EnumeratedFault<SpillNOther>
@@ -262,10 +255,8 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n)
{}
// These need to be handled specially to enable fill traps in SE
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class FillNOther : public EnumeratedFault<FillNOther>
@@ -281,10 +272,8 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n)
{}
// In SE, trap instructions are requesting services from the OS.
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
} // namespace SparcISA
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 6c9be8164..13f252e82 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -32,7 +32,6 @@
#include "arch/sparc/isa.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MiscRegs.hh"
@@ -136,12 +135,10 @@ ISA::clear()
nres_error_head = 0;
nres_error_tail = 0;
-#if FULL_SYSTEM
// If one of these events is active, it's not obvious to me how to get
// rid of it cleanly. For now we'll just assert that they're not.
if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
panic("Tick comparison event active when clearing the ISA object.\n");
-#endif
}
MiscReg
@@ -346,20 +343,8 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
case MISCREG_QUEUE_RES_ERROR_TAIL:
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
case MISCREG_HPSTATE:
return readFSReg(miscReg, tc);
-#else
- case MISCREG_HPSTATE:
- // HPSTATE is special because because sometimes in privilege
- // checks for instructions it will read HPSTATE to make sure
- // the priv. level is ok So, we'll just have to tell it it
- // isn't, instead of panicing.
- return 0;
-
- panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
-#endif
-
}
return readMiscRegNoEffect(miscReg);
}
@@ -569,12 +554,10 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
return;
case MISCREG_TL:
tl = val;
-#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
else
tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
return;
case MISCREG_CWP:
new_val = val >= NWindows ? NWindows - 1 : val;
@@ -610,18 +593,9 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
case MISCREG_QUEUE_RES_ERROR_TAIL:
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
case MISCREG_HPSTATE:
setFSReg(miscReg, val, tc);
return;
-#else
- case MISCREG_HPSTATE:
- // HPSTATE is special because normal trap processing saves HPSTATE when
- // it goes into a trap, and restores it when it returns.
- return;
- panic("Accessing Fullsystem register %d to %#x in SE mode\n",
- miscReg, val);
-#endif
}
setMiscRegNoEffect(miscReg, new_val);
}
@@ -667,7 +641,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
SERIALIZE_SCALAR(res_error_tail);
SERIALIZE_SCALAR(nres_error_head);
SERIALIZE_SCALAR(nres_error_tail);
-#if FULL_SYSTEM
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
ThreadContext *tc = NULL;
BaseCPU *cpu = NULL;
@@ -701,7 +674,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
SERIALIZE_SCALAR(stick_cmp);
SERIALIZE_SCALAR(hstick_cmp);
}
-#endif
}
void
@@ -747,7 +719,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(nres_error_head);
UNSERIALIZE_SCALAR(nres_error_tail);
-#if FULL_SYSTEM
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
ThreadContext *tc = NULL;
BaseCPU *cpu = NULL;
@@ -778,7 +749,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
}
}
- #endif
}
}
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index f00068bbc..e5d258786 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -36,7 +36,6 @@
#include "arch/sparc/registers.hh"
#include "arch/sparc/types.hh"
-#include "config/full_system.hh"
#include "cpu/cpuevent.hh"
class Checkpoint;
@@ -114,7 +113,6 @@ class ISA
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
-#if FULL_SYSTEM
void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
MiscReg readFSReg(int miscReg, ThreadContext * tc);
@@ -138,7 +136,6 @@ class ISA
typedef CpuEventWrapper<ISA,
&ISA::processHSTickCompare> HSTickCompareEvent;
HSTickCompareEvent *hSTickCompare;
-#endif
static const int NumGlobalRegs = 8;
static const int NumWindowedRegs = 24;
@@ -205,11 +202,9 @@ class ISA
ISA()
{
-#if FULL_SYSTEM
tickCompare = NULL;
sTickCompare = NULL;
hSTickCompare = NULL;
-#endif
clear();
}
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index a42c96ab1..d38df1c25 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -566,7 +566,7 @@ output exec {{
static inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
xc->readMiscReg(MISCREG_FPRS) & 0x4) {
return NoFault;
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 0ca56252e..a77059181 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -326,7 +326,7 @@ let {{
'''
TruncateEA = '''
- if (!FULL_SYSTEM)
+ if (!FullSystem)
EA = Pstate<3:> ? EA<31:0> : EA;
'''
}};
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 0c49cee16..541254d51 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -74,6 +74,7 @@ output exec {{
#include "debug/Sparc.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 620d9c402..9b02a4d80 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -35,7 +35,6 @@
#include "arch/sparc/sparc_traits.hh"
#include "arch/sparc/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace BigEndianGuest {}
@@ -78,7 +77,6 @@ const Addr VAddrAMask = ULL(0xFFFFFFFF);
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
const Addr BytesInPageMask = ULL(0x1FFF);
-#if FULL_SYSTEM
enum InterruptTypes
{
IT_TRAP_LEVEL_ZERO,
@@ -91,8 +89,6 @@ enum InterruptTypes
NumInterruptTypes
};
-#endif
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
}
diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 28e3ec259..c13fdc910 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -38,7 +38,6 @@
*/
#include "arch/sparc/tlb.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
@@ -48,21 +47,13 @@ namespace SparcISA
inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt)
{
-#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
}
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
-#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
}
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh
index 43320196b..aba17e505 100644
--- a/src/arch/sparc/pagetable.hh
+++ b/src/arch/sparc/pagetable.hh
@@ -36,7 +36,6 @@
#include "arch/sparc/isa_traits.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
class Checkpoint;
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index 712314e01..ece6ec963 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -127,7 +127,6 @@
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/GDBRead.hh"
@@ -135,6 +134,7 @@
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/system.hh"
@@ -156,18 +156,18 @@ RemoteGDB::acc(Addr va, size_t len)
//@Todo In NetBSD, this function checks if all addresses
// from va to va + len have valid page map entries. Not
// sure how this will work for other OSes or in general.
-#if FULL_SYSTEM
- if (va)
- return true;
- return false;
-#else
- TlbEntry entry;
- // Check to make sure the first byte is mapped into the processes address
- // space.
- if (context->getProcessPtr()->pTable->lookup(va, entry))
- return true;
- return false;
-#endif
+ if (FullSystem) {
+ if (va)
+ return true;
+ return false;
+ } else {
+ TlbEntry entry;
+ // Check to make sure the first byte is mapped into the processes
+ // address space.
+ if (context->getProcessPtr()->pTable->lookup(va, entry))
+ return true;
+ return false;
+ }
}
///////////////////////////////////////////////////////////
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index ddc37cf3b..a6179e0f8 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -42,6 +42,7 @@
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
/* @todo remove some of the magic constants. -- ali
@@ -497,14 +498,14 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
if (e == NULL || !e->valid) {
writeTagAccess(vaddr, context);
- if (real)
+ if (real) {
return new InstructionRealTranslationMiss;
- else
-#if FULL_SYSTEM
- return new FastInstructionAccessMMUMiss;
-#else
- return new FastInstructionAccessMMUMiss(req->getVaddr());
-#endif
+ } else {
+ if (FullSystem)
+ return new FastInstructionAccessMMUMiss;
+ else
+ return new FastInstructionAccessMMUMiss(req->getVaddr());
+ }
}
// were not priviledged accesing priv page
@@ -709,14 +710,14 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
if (e == NULL || !e->valid) {
writeTagAccess(vaddr, context);
DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
- if (real)
+ if (real) {
return new DataRealTranslationMiss;
- else
-#if FULL_SYSTEM
- return new FastDataAccessMMUMiss;
-#else
- return new FastDataAccessMMUMiss(req->getVaddr());
-#endif
+ } else {
+ if (FullSystem)
+ return new FastDataAccessMMUMiss;
+ else
+ return new FastDataAccessMMUMiss(req->getVaddr());
+ }
}
@@ -840,8 +841,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
-#if FULL_SYSTEM
-
Tick
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
@@ -1280,8 +1279,6 @@ doMmuWriteError:
return tc->getCpuPtr()->ticks(1);
}
-#endif
-
void
TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76ef23b64..cefa38175 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -34,7 +34,6 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "mem/request.hh"
#include "params/SparcTLB.hh"
#include "sim/fault_fwd.hh"
@@ -48,11 +47,9 @@ namespace SparcISA
class TLB : public BaseTLB
{
-#if !FULL_SYSTEM
// These faults need to be able to populate the tlb in SE mode.
friend class FastInstructionAccessMMUMiss;
friend class FastDataAccessMMUMiss;
-#endif
// TLB state
protected:
@@ -167,10 +164,8 @@ class TLB : public BaseTLB
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
-#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 67c17900b..e6ab64de9 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -36,6 +36,7 @@
#include "debug/Quiesce.hh"
#include "debug/Timer.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
using namespace SparcISA;
using namespace std;
@@ -207,12 +208,10 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
case MISCREG_HPSTATE:
// T1000 spec says impl. dependent val must always be 1
setMiscRegNoEffect(miscReg, val | HPSTATE::id);
-#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
else
cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
break;
case MISCREG_HTSTATE:
setMiscRegNoEffect(miscReg, val);
@@ -226,7 +225,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
// Time to go to sleep
tc->suspend();
- if (tc->getKernelStats())
+ if (FullSystem && tc->getKernelStats())
tc->getKernelStats()->quiesce();
}
break;
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index c6616f43e..63b8e7960 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -31,10 +31,8 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/utility.hh"
-#if FULL_SYSTEM
#include "arch/sparc/vtophys.hh"
#include "mem/vport.hh"
-#endif
namespace SparcISA {
@@ -48,21 +46,21 @@ namespace SparcISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
- const int NumArgumentRegs = 6;
- if (number < NumArgumentRegs) {
- return tc->readIntReg(8 + number);
+ if (FullSystem) {
+ const int NumArgumentRegs = 6;
+ if (number < NumArgumentRegs) {
+ return tc->readIntReg(8 + number);
+ } else {
+ Addr sp = tc->readIntReg(StackPointerReg);
+ VirtualPort *vp = tc->getVirtPort();
+ uint64_t arg = vp->read<uint64_t>(sp + 92 +
+ (number-NumArgumentRegs) * sizeof(uint64_t));
+ return arg;
+ }
} else {
- Addr sp = tc->readIntReg(StackPointerReg);
- VirtualPort *vp = tc->getVirtPort();
- uint64_t arg = vp->read<uint64_t>(sp + 92 +
- (number-NumArgumentRegs) * sizeof(uint64_t));
- return arg;
+ panic("getArgument() only implemented for full system\n");
+ M5_DUMMY_RETURN
}
-#else
- panic("getArgument() only implemented for FULL_SYSTEM\n");
- M5_DUMMY_RETURN
-#endif
}
void
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 76b551ac8..ee94ef29a 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -39,6 +39,7 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/fault_fwd.hh"
+#include "sim/full_system.hh"
namespace SparcISA
{
@@ -73,13 +74,9 @@ void initCPU(ThreadContext *tc, int cpuId);
inline void
startupCPU(ThreadContext *tc, int cpuId)
{
-#if FULL_SYSTEM
// Other CPUs will get activated by IPIs
- if (cpuId == 0)
+ if (cpuId == 0 || !FullSystem)
tc->activate(0);
-#else
- tc->activate(0);
-#endif
}
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 2742c79e8..3bd968e21 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -53,45 +53,38 @@ if env['TARGET_ISA'] == 'x86':
Source('insts/microop.cc')
Source('insts/microregop.cc')
Source('insts/static_inst.cc')
+ Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/syscalls.cc')
+ Source('linux/system.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
+ Source('pagetable_walker.cc')
Source('predecoder.cc')
Source('predecoder_tables.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
Source('tlb.cc')
Source('types.cc')
Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('X86LocalApic.py')
SimObject('X86NativeTrace.py')
-
+ SimObject('X86System.py')
SimObject('X86TLB.py')
+
+ DebugFlag('Faults', "Trace all faults/exceptions/traps")
+ DebugFlag('LocalApic', "Local APIC debugging")
+ DebugFlag('PageTableWalker', \
+ "Page table walker state machine debugging")
DebugFlag('Predecoder', "Predecoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
- if env['FULL_SYSTEM']:
- DebugFlag('LocalApic', "Local APIC debugging")
- DebugFlag('PageTableWalker', \
- "Page table walker state machine debugging")
- DebugFlag('Faults', "Trace all faults/exceptions/traps")
-
- SimObject('X86LocalApic.py')
- SimObject('X86System.py')
-
- # Full-system sources
- Source('interrupts.cc')
- Source('linux/system.cc')
- Source('pagetable_walker.cc')
- Source('system.cc')
- Source('stacktrace.cc')
- Source('vtophys.cc')
- else:
- Source('process.cc')
-
- Source('linux/linux.cc')
- Source('linux/process.cc')
- Source('linux/syscalls.cc')
-
python_files = (
'__init__.py',
'general_purpose/__init__.py',
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index b9be19b64..2f53c4e24 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -26,7 +26,9 @@
#
# Authors: Gabe Black
+from m5.defines import buildEnv
from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice
class X86LocalApic(BasicPioDevice):
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index ae9bfd353..7f2fcd358 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -35,24 +35,21 @@
#
# Authors: Gabe Black
-from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from BaseTLB import BaseTLB
from MemObject import MemObject
-if buildEnv['FULL_SYSTEM']:
- class X86PagetableWalker(MemObject):
- type = 'X86PagetableWalker'
- cxx_class = 'X86ISA::Walker'
- port = Port("Port for the hardware table walker")
- system = Param.System(Parent.any, "system object")
+class X86PagetableWalker(MemObject):
+ type = 'X86PagetableWalker'
+ cxx_class = 'X86ISA::Walker'
+ port = Port("Port for the hardware table walker")
+ system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
size = Param.Int(64, "TLB size")
- if buildEnv['FULL_SYSTEM']:
- walker = Param.X86PagetableWalker(\
- X86PagetableWalker(), "page table walker")
+ walker = Param.X86PagetableWalker(\
+ X86PagetableWalker(), "page table walker")
diff --git a/src/arch/x86/bios/SConscript b/src/arch/x86/bios/SConscript
index 16a413ed0..abc734ef4 100644
--- a/src/arch/x86/bios/SConscript
+++ b/src/arch/x86/bios/SConscript
@@ -40,20 +40,19 @@
Import('*')
if env['TARGET_ISA'] == 'x86':
- if env['FULL_SYSTEM']:
- # The table generated by the bootloader using the BIOS and passed to
- # the operating system which maps out physical memory.
- SimObject('E820.py')
- Source('e820.cc')
+ # The table generated by the bootloader using the BIOS and passed to
+ # the operating system which maps out physical memory.
+ SimObject('E820.py')
+ Source('e820.cc')
- # The DMI tables.
- SimObject('SMBios.py')
- Source('smbios.cc')
+ # The DMI tables.
+ SimObject('SMBios.py')
+ Source('smbios.cc')
- # Intel Multiprocessor Specification Configuration Table
- SimObject('IntelMP.py')
- Source('intelmp.cc')
+ # Intel Multiprocessor Specification Configuration Table
+ SimObject('IntelMP.py')
+ Source('intelmp.cc')
- # ACPI system description tables
- SimObject('ACPI.py')
- Source('acpi.cc')
+ # ACPI system description tables
+ SimObject('ACPI.py')
+ Source('acpi.cc')
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index feb88fd76..e49bbdbac 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -42,56 +42,53 @@
#include "arch/x86/decoder.hh"
#include "arch/x86/faults.hh"
+#include "arch/x86/isa_traits.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
-#include "arch/x86/isa_traits.hh"
-#include "mem/page_table.hh"
-#include "sim/process.hh"
-#else
-#include "arch/x86/tlb.hh"
#include "debug/Faults.hh"
-#endif
+#include "sim/full_system.hh"
namespace X86ISA
{
-#if FULL_SYSTEM
void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
- PCState pcState = tc->pcState();
- Addr pc = pcState.pc();
- DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
- using namespace X86ISAInst::RomLabels;
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- MicroPC entry;
- if (m5reg.mode == LongMode) {
- if (isSoft()) {
- entry = extern_label_longModeSoftInterrupt;
- } else {
- entry = extern_label_longModeInterrupt;
- }
- } else {
- entry = extern_label_legacyModeInterrupt;
- }
- tc->setIntReg(INTREG_MICRO(1), vector);
- tc->setIntReg(INTREG_MICRO(7), pc);
- if (errorCode != (uint64_t)(-1)) {
+ if (FullSystem) {
+ PCState pcState = tc->pcState();
+ Addr pc = pcState.pc();
+ DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
+ pc, vector, describe());
+ using namespace X86ISAInst::RomLabels;
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ MicroPC entry;
if (m5reg.mode == LongMode) {
- entry = extern_label_longModeInterruptWithError;
+ if (isSoft()) {
+ entry = extern_label_longModeSoftInterrupt;
+ } else {
+ entry = extern_label_longModeInterrupt;
+ }
} else {
- panic("Legacy mode interrupts with error codes "
- "aren't implementde.\n");
+ entry = extern_label_legacyModeInterrupt;
+ }
+ tc->setIntReg(INTREG_MICRO(1), vector);
+ tc->setIntReg(INTREG_MICRO(7), pc);
+ if (errorCode != (uint64_t)(-1)) {
+ if (m5reg.mode == LongMode) {
+ entry = extern_label_longModeInterruptWithError;
+ } else {
+ panic("Legacy mode interrupts with error codes "
+ "aren't implementde.\n");
+ }
+ // Software interrupts shouldn't have error codes. If one
+ // does, there would need to be microcode to set it up.
+ assert(!isSoft());
+ tc->setIntReg(INTREG_MICRO(15), errorCode);
}
- // Software interrupts shouldn't have error codes. If one does,
- // there would need to be microcode to set it up.
- assert(!isSoft());
- tc->setIntReg(INTREG_MICRO(15), errorCode);
+ pcState.upc(romMicroPC(entry));
+ pcState.nupc(romMicroPC(entry) + 1);
+ tc->pcState(pcState);
+ } else {
+ FaultBase::invoke(tc, inst);
}
- pcState.upc(romMicroPC(entry));
- pcState.nupc(romMicroPC(entry) + 1);
- tc->pcState(pcState);
}
std::string
@@ -109,9 +106,12 @@ namespace X86ISA
void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
{
X86FaultBase::invoke(tc);
- // This is the same as a fault, but it happens -after- the instruction.
- PCState pc = tc->pcState();
- pc.uEnd();
+ if (FullSystem) {
+ // This is the same as a fault, but it happens -after- the
+ // instruction.
+ PCState pc = tc->pcState();
+ pc.uEnd();
+ }
}
void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
@@ -119,19 +119,43 @@ namespace X86ISA
panic("Abort exception!");
}
+ void
+ InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
+ {
+ if (FullSystem) {
+ X86Fault::invoke(tc, inst);
+ } else {
+ panic("Unrecognized/invalid instruction executed:\n %s",
+ inst->machInst);
+ }
+ }
+
void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
{
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- X86FaultBase::invoke(tc);
- /*
- * If something bad happens while trying to enter the page fault
- * handler, I'm pretty sure that's a double fault and then all bets are
- * off. That means it should be safe to update this state now.
- */
- if (m5reg.mode == LongMode) {
- tc->setMiscReg(MISCREG_CR2, addr);
+ if (FullSystem) {
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ X86FaultBase::invoke(tc);
+ /*
+ * If something bad happens while trying to enter the page fault
+ * handler, I'm pretty sure that's a double fault and then all
+ * bets are off. That means it should be safe to update this
+ * state now.
+ */
+ if (m5reg.mode == LongMode) {
+ tc->setMiscReg(MISCREG_CR2, addr);
+ } else {
+ tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+ }
} else {
- tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+ PageFaultErrorCode code = errorCode;
+ const char *modeStr = "";
+ if (code.fetch)
+ modeStr = "execute";
+ else if (code.write)
+ modeStr = "write";
+ else
+ modeStr = "read";
+ panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
}
}
@@ -268,30 +292,5 @@ namespace X86ISA
tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
}
-
-#else
-
- void
- InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
- {
- panic("Unrecognized/invalid instruction executed:\n %s",
- inst->machInst);
- }
-
- void
- PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
- {
- PageFaultErrorCode code = errorCode;
- const char *modeStr = "";
- if (code.fetch)
- modeStr = "execute";
- else if (code.write)
- modeStr = "write";
- else
- modeStr = "read";
- panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
- }
-
-#endif
} // namespace X86ISA
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index fba2a26b5..94a2ffcc2 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -85,12 +85,10 @@ namespace X86ISA
return false;
}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
virtual std::string describe() const;
-#endif
};
// Base class for x86 faults which behave as if the underlying instruction
@@ -114,10 +112,8 @@ namespace X86ISA
: X86FaultBase(name, mnem, vector, _errorCode)
{}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
// Base class for x86 aborts which seem to be catastrophic failures.
@@ -129,10 +125,8 @@ namespace X86ISA
: X86FaultBase(name, mnem, vector, _errorCode)
{}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
// Base class for x86 interrupts.
@@ -246,10 +240,8 @@ namespace X86ISA
X86Fault("Invalid-Opcode", "#UD", 6)
{}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class DeviceNotAvailable : public X86Fault
@@ -334,9 +326,7 @@ namespace X86ISA
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#if FULL_SYSTEM
virtual std::string describe() const;
-#endif
};
class X87FpExceptionPending : public X86Fault
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 7d6f6e35e..28f1ac04d 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -47,6 +47,7 @@
#include "dev/x86/south_bridge.hh"
#include "mem/packet_access.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
int
divideFromConf(uint32_t conf)
@@ -273,8 +274,9 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector,
pendingUnmaskableInt = pendingStartup = true;
startupVector = vector;
}
- }
- cpu->wakeup();
+ }
+ if (FullSystem)
+ cpu->wakeup();
}
@@ -302,10 +304,6 @@ X86ISA::Interrupts::init()
//
BasicPioDevice::init();
IntDev::init();
-
- Pc * pc = dynamic_cast<Pc *>(platform);
- assert(pc);
- pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
}
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index f5d86219b..389eb4f42 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -176,6 +176,9 @@ class Interrupts : public BasicPioDevice, IntDev
int initialApicId;
public:
+
+ int getInitialApicId() { return initialApicId; }
+
/*
* Params stuff.
*/
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 4a5cf32d0..4ebf23032 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -394,7 +394,7 @@
default: Inst::RET_FAR();
}
0x4: int3();
- 0x5: decode FULL_SYSTEM default int_Ib() {
+ 0x5: decode FullSystem default int_Ib() {
0: decode IMMEDIATE {
// Really only the LSB matters, but the predecoder
// will sign extend it, and there's no easy way to
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 2471b61ce..030e36404 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -216,7 +216,7 @@
default: Inst::UD2();
}
}
- 0x05: decode FULL_SYSTEM {
+ 0x05: decode FullSystem {
0: SyscallInst::syscall('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: decode MODE_MODE {
@@ -398,7 +398,7 @@
0x1: Inst::RDTSC();
0x2: Inst::RDMSR();
0x3: rdpmc();
- 0x4: decode FULL_SYSTEM {
+ 0x4: decode FullSystem {
0: SyscallInst::sysenter('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: sysenter();
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 237b29877..9a9759c7a 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -84,6 +84,7 @@ output decoder {{
#include "base/misc.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+#include "sim/full_system.hh"
#if defined(linux) || defined(__APPLE__)
#include <fenv.h>
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 525f54bfb..054f280a8 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -47,7 +47,6 @@
*/
#include "arch/x86/regs/misc.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
@@ -57,25 +56,18 @@ namespace X86ISA
inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt)
{
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data = htog(xc->readMiscReg(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->setData(((uint8_t *)&data) + offset);
-#endif
return xc->getCpuPtr()->ticks(1);
}
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data;
@@ -84,7 +76,6 @@ namespace X86ISA
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->writeData(((uint8_t *)&data) + offset);
xc->setMiscReg(index, gtoh(data));
-#endif
return xc->getCpuPtr()->ticks(1);
}
};
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 8db7a6088..c7bce59bf 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -47,7 +47,6 @@
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
using namespace std;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 40c30637d..53f7f978e 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -44,23 +44,19 @@
#include "arch/x86/regs/msr.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/pagetable.hh"
+#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
-#include "mem/request.hh"
-
-#if FULL_SYSTEM
-#include "arch/x86/pagetable_walker.hh"
-#else
#include "mem/page_table.hh"
+#include "mem/request.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
-#endif
namespace X86ISA {
@@ -72,10 +68,8 @@ TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
for (int x = 0; x < size; x++)
freeList.push_back(&tlb[x]);
-#if FULL_SYSTEM
walker = p->walker;
walker->setTLB(this);
-#endif
}
TlbEntry *
@@ -293,40 +287,40 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
if (!entry) {
-#if FULL_SYSTEM
- Fault fault = walker->start(tc, translation, req, mode);
- if (timing || fault != NoFault) {
- // This gets ignored in atomic mode.
- delayedResponse = true;
- return fault;
- }
- entry = lookup(vaddr);
- assert(entry);
-#else
- DPRINTF(TLB, "Handling a TLB miss for "
- "address %#x at pc %#x.\n",
- vaddr, tc->instAddr());
-
- Process *p = tc->getProcessPtr();
- TlbEntry newEntry;
- bool success = p->pTable->lookup(vaddr, newEntry);
- if (!success && mode != Execute) {
- // Check if we just need to grow the stack.
- if (p->fixupStackFault(vaddr)) {
- // If we did, lookup the entry for the new page.
- success = p->pTable->lookup(vaddr, newEntry);
+ if (FullSystem) {
+ Fault fault = walker->start(tc, translation, req, mode);
+ if (timing || fault != NoFault) {
+ // This gets ignored in atomic mode.
+ delayedResponse = true;
+ return fault;
}
- }
- if (!success) {
- return new PageFault(vaddr, true, mode, true, false);
+ entry = lookup(vaddr);
+ assert(entry);
} else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
- newEntry.pageStart());
- entry = insert(alignedVaddr, newEntry);
+ DPRINTF(TLB, "Handling a TLB miss for "
+ "address %#x at pc %#x.\n",
+ vaddr, tc->instAddr());
+
+ Process *p = tc->getProcessPtr();
+ TlbEntry newEntry;
+ bool success = p->pTable->lookup(vaddr, newEntry);
+ if (!success && mode != Execute) {
+ // Check if we just need to grow the stack.
+ if (p->fixupStackFault(vaddr)) {
+ // If we did, lookup the entry for the new page.
+ success = p->pTable->lookup(vaddr, newEntry);
+ }
+ }
+ if (!success) {
+ return new PageFault(vaddr, true, mode, true, false);
+ } else {
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
+ newEntry.pageStart());
+ entry = insert(alignedVaddr, newEntry);
+ }
+ DPRINTF(TLB, "Miss was serviced.\n");
}
- DPRINTF(TLB, "Miss was serviced.\n");
-#endif
}
// Do paging protection checks.
bool inUser = (m5Reg.cpl == 3 &&
@@ -366,27 +360,29 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
req->setPaddr(vaddr);
}
// Check for an access to the local APIC
-#if FULL_SYSTEM
- LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
- Addr baseAddr = localApicBase.base * PageBytes;
- Addr paddr = req->getPaddr();
- if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
- // The Intel developer's manuals say the below restrictions apply,
- // but the linux kernel, because of a compiler optimization, breaks
- // them.
- /*
- // Check alignment
- if (paddr & ((32/8) - 1))
- return new GeneralProtection(0);
- // Check access size
- if (req->getSize() != (32/8))
- return new GeneralProtection(0);
- */
- // Force the access to be uncacheable.
- req->setFlags(Request::UNCACHEABLE);
- req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
+ if (FullSystem) {
+ LocalApicBase localApicBase =
+ tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
+ Addr baseAddr = localApicBase.base * PageBytes;
+ Addr paddr = req->getPaddr();
+ if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
+ // The Intel developer's manuals say the below restrictions apply,
+ // but the linux kernel, because of a compiler optimization, breaks
+ // them.
+ /*
+ // Check alignment
+ if (paddr & ((32/8) - 1))
+ return new GeneralProtection(0);
+ // Check access size
+ if (req->getSize() != (32/8))
+ return new GeneralProtection(0);
+ */
+ // Force the access to be uncacheable.
+ req->setFlags(Request::UNCACHEABLE);
+ req->setPaddr(x86LocalAPICAddress(tc->contextId(),
+ paddr - baseAddr));
+ }
}
-#endif
return NoFault;
};
@@ -409,28 +405,12 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(fault, req, tc, mode);
}
-#if FULL_SYSTEM
-
-Tick
-TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
-{
- return tc->getCpuPtr()->ticks(1);
-}
-
-Tick
-TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
-{
- return tc->getCpuPtr()->ticks(1);
-}
-
Walker *
TLB::getWalker()
{
return walker;
}
-#endif
-
void
TLB::serialize(std::ostream &os)
{
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index e4ea0e1b7..449ca19ce 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -46,7 +46,6 @@
#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
-#include "config/full_system.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
@@ -85,15 +84,11 @@ namespace X86ISA
EntryList::iterator lookupIt(Addr va, bool update_lru = true);
-#if FULL_SYSTEM
- protected:
-
Walker * walker;
+
public:
Walker *getWalker();
-#endif
- public:
void invalidateAll();
void invalidateNonGlobal();
@@ -120,11 +115,6 @@ namespace X86ISA
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
-#if FULL_SYSTEM
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
-
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 29c770f3d..678467672 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -38,11 +38,7 @@
* Authors: Gabe Black
*/
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
#include "arch/x86/interrupts.hh"
-#endif
#include "arch/x86/registers.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/utility.hh"
@@ -55,15 +51,10 @@ namespace X86ISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
panic("getArgument() not implemented for x86!\n");
-#else
- panic("getArgument() only implemented for FULL_SYSTEM\n");
M5_DUMMY_RETURN
-#endif
}
-# if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
@@ -193,12 +184,9 @@ void initCPU(ThreadContext *tc, int cpuId)
tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
}
-#endif
-
void startupCPU(ThreadContext *tc, int cpuId)
{
-#if FULL_SYSTEM
- if (cpuId == 0) {
+ if (cpuId == 0 || !FullSystem) {
tc->activate(0);
} else {
// This is an application processor (AP). It should be initialized to
@@ -206,9 +194,6 @@ void startupCPU(ThreadContext *tc, int cpuId)
// a halted state.
tc->suspend(0);
}
-#else
- tc->activate(0);
-#endif
}
void
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 4cfbe77db..f120ea6c7 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -45,9 +45,9 @@
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
class ThreadContext;
@@ -68,12 +68,12 @@ namespace X86ISA
static inline bool
inUserMode(ThreadContext *tc)
{
-#if FULL_SYSTEM
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- return m5reg.cpl == 3;
-#else
- return true;
-#endif
+ if (!FullSystem) {
+ return true;
+ } else {
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ return m5reg.cpl == 3;
+ }
}
/**
@@ -83,12 +83,8 @@ namespace X86ISA
template <class TC>
void zeroRegisters(TC *tc);
-#if FULL_SYSTEM
-
void initCPU(ThreadContext *tc, int cpuId);
-#endif
-
void startupCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
index 60ce37131..e4abfca59 100644
--- a/src/arch/x86/vtophys.cc
+++ b/src/arch/x86/vtophys.cc
@@ -43,7 +43,6 @@
#include "arch/x86/tlb.hh"
#include "arch/x86/vtophys.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "debug/VtoPhys.hh"
#include "sim/fault_fwd.hh"
@@ -55,16 +54,12 @@ namespace X86ISA
Addr
vtophys(Addr vaddr)
{
-#if FULL_SYSTEM
panic("Need access to page tables\n");
-#endif
- return vaddr;
}
Addr
vtophys(ThreadContext *tc, Addr vaddr)
{
-#if FULL_SYSTEM
Walker *walker = tc->getDTBPtr()->getWalker();
Addr size;
Addr addr = vaddr;
@@ -75,7 +70,5 @@ namespace X86ISA
Addr paddr = addr | masked_addr;
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
-#endif
- return vaddr;
}
}