diff options
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/isa_traits.hh | 3 | ||||
-rw-r--r-- | src/arch/arm/isa_traits.hh | 3 | ||||
-rw-r--r-- | src/arch/mips/isa_traits.hh | 3 | ||||
-rw-r--r-- | src/arch/power/isa_traits.hh | 3 | ||||
-rw-r--r-- | src/arch/sparc/isa_traits.hh | 3 | ||||
-rw-r--r-- | src/arch/x86/isa_traits.hh | 3 |
6 files changed, 18 insertions, 0 deletions
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 66c240ef3..a5a8bf5a0 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -131,6 +131,9 @@ enum { // Alpha UNOP (ldq_u r31,0(r0)) const ExtMachInst NoopMachInst = 0x2ffe0000; +// Memory accesses cannot be unaligned +const bool HasUnalignedMemAcc = false; + } // namespace AlphaISA #endif // __ARCH_ALPHA_ISA_TRAITS_HH__ diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh index 91c51c46b..59eaeaa5c 100644 --- a/src/arch/arm/isa_traits.hh +++ b/src/arch/arm/isa_traits.hh @@ -106,6 +106,9 @@ namespace ArmISA const int ByteBytes = 1; const uint32_t HighVecs = 0xFFFF0000; + + // Memory accesses cannot be unaligned + const bool HasUnalignedMemAcc = false; }; using namespace ArmISA; diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index 38b43af9d..aa64be71d 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -164,6 +164,9 @@ const int ByteBytes = 1; const int ANNOTE_NONE = 0; const uint32_t ITOUCH_ANNOTE = 0xffffffff; +// Memory accesses cannot be unaligned +const bool HasUnalignedMemAcc = false; + }; #endif // __ARCH_MIPS_ISA_TRAITS_HH__ diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh index 886c2cb0b..ab6a56760 100644 --- a/src/arch/power/isa_traits.hh +++ b/src/arch/power/isa_traits.hh @@ -70,6 +70,9 @@ const int MachineBytes = 4; // This is ori 0, 0, 0 const ExtMachInst NoopMachInst = 0x60000000; +// Memory accesses can be unaligned +const bool HasUnalignedMemAcc = true; + } // PowerISA namespace #endif // __ARCH_POWER_ISA_TRAITS_HH__ diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 2af624d39..a4dc7322d 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -98,6 +98,9 @@ namespace SparcISA }; #endif + +// Memory accesses cannot be unaligned +const bool HasUnalignedMemAcc = false; } #endif // __ARCH_SPARC_ISA_TRAITS_HH__ diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 9f1b7b7c4..80af12c91 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -91,6 +91,9 @@ namespace X86ISA StaticInstPtr decodeInst(ExtMachInst); const Addr LoadAddrMask = ULL(-1); + + // Memory accesses can be unaligned + const bool HasUnalignedMemAcc = true; }; #endif // __ARCH_X86_ISATRAITS_HH__ |