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-rw-r--r--src/arch/alpha/isa/main.isa2
-rw-r--r--src/arch/alpha/mt.hh1
-rw-r--r--src/arch/arm/isa/includes.isa2
-rw-r--r--src/arch/arm/types.hh4
-rw-r--r--src/arch/mips/isa/includes.isa4
-rw-r--r--src/arch/power/isa/includes.isa2
-rw-r--r--src/arch/power/types.hh4
-rw-r--r--src/arch/sparc/isa/decoder.isa8
-rw-r--r--src/arch/sparc/mt.hh1
-rw-r--r--src/arch/sparc/tlb_map.hh2
-rw-r--r--src/arch/x86/isa/microops/fpop.isa2
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa4
-rw-r--r--src/arch/x86/types.hh4
13 files changed, 18 insertions, 22 deletions
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 163e0a26f..5285d0572 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -70,7 +70,7 @@ using namespace AlphaISA;
}};
output exec {{
-#include <math.h>
+#include <cmath>
#include "arch/alpha/registers.hh"
#include "arch/alpha/regredir.hh"
diff --git a/src/arch/alpha/mt.hh b/src/arch/alpha/mt.hh
index 03ecf8486..cce27303a 100644
--- a/src/arch/alpha/mt.hh
+++ b/src/arch/alpha/mt.hh
@@ -44,7 +44,6 @@
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-using namespace std;
namespace AlphaISA
{
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index bfd6fedd4..607a5c8b8 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -94,6 +94,6 @@ output exec {{
#include "sim/sim_exit.hh"
using namespace ArmISA;
-using std::isnan;
+
}};
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 15f9f4d0a..31dec7bcb 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -540,13 +540,13 @@ namespace ArmISA
} // namespace ArmISA
-namespace __hash_namespace {
+__hash_namespace_begin
template<>
struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
size_t operator()(const ArmISA::ExtMachInst &emi) const {
return hash<uint32_t>::operator()((uint32_t)emi);
};
};
-}
+__hash_namespace_end
#endif
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index d2e9c797e..ac9945b09 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -45,7 +45,7 @@ output header {{
}};
output decoder {{
-#include <math.h>
+#include <cmath>
#include "arch/mips/dsp.hh"
#include "arch/mips/dt_constants.hh"
@@ -69,7 +69,7 @@ using namespace MipsISA;
}};
output exec {{
-#include <math.h>
+#include <cmath>
#include "arch/generic/memhelpers.hh"
#include "arch/mips/dsp.hh"
diff --git a/src/arch/power/isa/includes.isa b/src/arch/power/isa/includes.isa
index f6292eaab..ed2076d62 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -66,7 +66,6 @@ output decoder {{
#include "cpu/thread_context.hh"
using namespace PowerISA;
-using std::isnan;
}};
output exec {{
@@ -87,6 +86,5 @@ output exec {{
#include "sim/sim_exit.hh"
using namespace PowerISA;
-using std::isnan;
}};
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index 071b4b439..a5d204827 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -89,7 +89,7 @@ typedef GenericISA::SimplePCState<MachInst> PCState;
} // PowerISA namespace
-namespace __hash_namespace {
+__hash_namespace_begin
template<>
struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
@@ -98,6 +98,6 @@ struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
};
};
-} // namespace __hash_namespace
+__hash_namespace_end
#endif // __ARCH_POWER_TYPES_HH__
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 44d2643c6..ad8ba5300 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -683,7 +683,7 @@ decode OP default Unknown::unknown()
0x47: FpUnimpl::fmovrqlez();
0x51: fcmps({{
uint8_t fcc;
- if (isnan(Frs1s) || isnan(Frs2s))
+ if (std::isnan(Frs1s) || std::isnan(Frs2s))
fcc = 3;
else if (Frs1s < Frs2s)
fcc = 1;
@@ -698,7 +698,7 @@ decode OP default Unknown::unknown()
}});
0x52: fcmpd({{
uint8_t fcc;
- if (isnan(Frs1) || isnan(Frs2))
+ if (std::isnan(Frs1) || std::isnan(Frs2))
fcc = 3;
else if (Frs1 < Frs2)
fcc = 1;
@@ -714,7 +714,7 @@ decode OP default Unknown::unknown()
0x53: FpUnimpl::fcmpq();
0x55: fcmpes({{
uint8_t fcc = 0;
- if (isnan(Frs1s) || isnan(Frs2s))
+ if (std::isnan(Frs1s) || std::isnan(Frs2s))
fault = new FpExceptionIEEE754;
if (Frs1s < Frs2s)
fcc = 1;
@@ -727,7 +727,7 @@ decode OP default Unknown::unknown()
}});
0x56: fcmped({{
uint8_t fcc = 0;
- if (isnan(Frs1) || isnan(Frs2))
+ if (std::isnan(Frs1) || std::isnan(Frs2))
fault = new FpExceptionIEEE754;
if (Frs1 < Frs2)
fcc = 1;
diff --git a/src/arch/sparc/mt.hh b/src/arch/sparc/mt.hh
index 8b3d97aad..7fb054902 100644
--- a/src/arch/sparc/mt.hh
+++ b/src/arch/sparc/mt.hh
@@ -44,7 +44,6 @@
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-using namespace std;
namespace SparcISA
{
diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh
index 5541ff7e9..c09e6eb95 100644
--- a/src/arch/sparc/tlb_map.hh
+++ b/src/arch/sparc/tlb_map.hh
@@ -98,7 +98,7 @@ class TlbMap
if (intersect(r))
return tree.end();
- return tree.insert(std::make_pair<TlbRange,TlbEntry*>(r, d)).first;
+ return tree.insert(std::make_pair(r, d)).first;
}
size_t
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index 17698f198..01f26b0f5 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -285,7 +285,7 @@ let {{
// OF = SF = AF = 0
ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit |
ZFBit | PFBit | CFBit);
- if (isnan(FpSrcReg1) || isnan(FpSrcReg2))
+ if (std::isnan(FpSrcReg1) || std::isnan(FpSrcReg2))
ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit);
else if(FpSrcReg1 < FpSrcReg2)
ccFlagBits = ccFlagBits | CFBit;
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 9320d9f39..0c4827990 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -1404,7 +1404,7 @@ let {{
}
uint64_t resBits = 0;
- bool nanop = isnan(arg1) || isnan(arg2);
+ bool nanop = std::isnan(arg1) || std::isnan(arg2);
switch (ext & mask(3)) {
case 0:
if (arg1 == arg2 && !nanop)
@@ -1492,7 +1492,7 @@ let {{
// OF = SF = AF = 0
ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit |
ZFBit | PFBit | CFBit);
- if (isnan(arg1) || isnan(arg2))
+ if (std::isnan(arg1) || std::isnan(arg2))
ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit);
else if(arg1 < arg2)
ccFlagBits = ccFlagBits | CFBit;
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index c7e824fb7..6d9f600ff 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -280,7 +280,7 @@ namespace X86ISA
}
-namespace __hash_namespace {
+__hash_namespace_begin
template<>
struct hash<X86ISA::ExtMachInst> {
size_t operator()(const X86ISA::ExtMachInst &emi) const {
@@ -298,7 +298,7 @@ namespace __hash_namespace {
emi.stackSize ^ emi.dispSize;
};
};
-}
+__hash_namespace_end
// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
// and UNSERIALIZE_SCALAR.
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-13 21:57:35 +0000