summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/sparc/isa/base.isa70
-rw-r--r--src/arch/sparc/isa/formats/basic.isa2
-rw-r--r--src/arch/sparc/isa/formats/mem/basicmem.isa4
-rw-r--r--src/arch/sparc/isa/formats/mem/blockmem.isa2
-rw-r--r--src/arch/sparc/isa/formats/micro.isa33
-rw-r--r--src/arch/sparc/isa/operands.isa54
-rw-r--r--src/arch/x86/faults.hh20
-rw-r--r--src/arch/x86/isa/base.isa32
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa22
-rw-r--r--src/arch/x86/isa/formats/multi.isa4
-rw-r--r--src/arch/x86/isa/macroop.isa51
-rw-r--r--src/arch/x86/isa/microasm.isa21
-rw-r--r--src/arch/x86/isa/microops/base.isa49
-rw-r--r--src/arch/x86/isa/microops/microops.isa3
-rw-r--r--src/arch/x86/isa/specialize.isa38
15 files changed, 320 insertions, 85 deletions
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index bba63f407..4339003e0 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -154,6 +154,76 @@ def template ROrImmDecode {{
}
}};
+output header {{
+ union DoubleSingle
+ {
+ double d;
+ uint64_t ui;
+ uint32_t s[2];
+ DoubleSingle(double _d) : d(_d)
+ {}
+ DoubleSingle(uint64_t _ui) : ui(_ui)
+ {}
+ DoubleSingle(uint32_t _s0, uint32_t _s1)
+ {
+ s[0] = _s0;
+ s[1] = _s1;
+ }
+ };
+}};
+
+let {{
+ def filterDoubles(code):
+ assignRE = re.compile(r'\s*=(?!=)', re.MULTILINE)
+ for opName in ("Frd", "Frs1", "Frs2", "Frd_N"):
+ next_pos = 0
+ operandsREString = (r'''
+ (?<![\w\.]) # neg. lookbehind assertion: prevent partial matches
+ ((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix
+ (?![\w\.]) # neg. lookahead assertion: prevent partial matches
+ ''' % opName)
+ operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
+ is_src = False
+ is_dest = False
+ extension = None
+ foundOne = False
+ while 1:
+ match = operandsRE.search(code, next_pos)
+ if not match:
+ break
+ foundOne = True
+ op = match.groups()
+ (op_full, op_base, op_ext) = op
+ is_dest_local = (assignRE.match(code, match.end()) != None)
+ is_dest = is_dest or is_dest_local
+ is_src = is_src or not is_dest_local
+ if extension and extension != op_ext:
+ raise Exception, "Inconsistent extensions in double filter."
+ extension = op_ext
+ next_pos = match.end()
+ if foundOne:
+ # Get rid of any unwanted extension
+ code = operandsRE.sub(op_base, code)
+ is_int = False
+ member = "d"
+ if extension in ("sb", "ub", "shw", "uhw", "sw", "uw", "sdw", "udw"):
+ is_int = True
+ member = "ui"
+ if is_src:
+ code = ("%s = DoubleSingle(%s_high, %s_low).%s;" % \
+ (opName, opName, opName, member)) + code
+ if is_dest:
+ code += '''
+ %s_low = DoubleSingle(%s).s[1];
+ %s_high = DoubleSingle(%s).s[0];''' % \
+ (opName, opName, opName, opName)
+ if is_int:
+ code = ("uint64_t %s;" % opName) + code
+ else:
+ code = ("double %s;" % opName) + code
+ return code
+}};
+
let {{
def splitOutImm(code):
matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?')
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 017f43780..7665d2d4f 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -97,6 +97,7 @@ def template BasicDecodeWithMnemonic {{
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
+ code = filterDoubles(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -140,6 +141,7 @@ def format FpBasic(code, *flags) {{
fesetround(oldrnd);
#endif
"""
+ fp_code = filterDoubles(fp_code)
iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 751262811..2f62c7bef 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -71,6 +71,7 @@ let {{
}};
def format LoadAlt(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
@@ -79,6 +80,7 @@ def format LoadAlt(code, asi, *opt_flags) {{
}};
def format StoreAlt(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
@@ -87,6 +89,7 @@ def format StoreAlt(code, asi, *opt_flags) {{
}};
def format Load(code, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
@@ -95,6 +98,7 @@ def format Load(code, *opt_flags) {{
}};
def format Store(code, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 499685a5c..e19016bd0 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -317,6 +317,7 @@ let {{
}};
def format BlockLoad(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
# We need to make sure to check the highest priority fault last.
# That way, if other faults have been detected, they'll be overwritten
# rather than the other way around.
@@ -329,6 +330,7 @@ def format BlockLoad(code, asi, *opt_flags) {{
}};
def format BlockStore(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
# We need to make sure to check the highest priority fault last.
# That way, if other faults have been detected, they'll be overwritten
# rather than the other way around.
diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa
index 82d7fb4cb..da0f97d1b 100644
--- a/src/arch/sparc/isa/formats/micro.isa
+++ b/src/arch/sparc/isa/formats/micro.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -26,6 +26,33 @@
//
// Authors: Gabe Black
+//This delcares the initiateAcc function in memory operations
+def template MacroInitiateAcc {{
+ Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ {
+ panic("Tried to execute a macroop directly!\n");
+ return NoFault;
+ }
+}};
+
+def template MacroCompleteAcc {{
+ Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
+ Trace::InstRecord *) const
+ {
+ panic("Tried to execute a macroop directly!\n");
+ return NoFault;
+ }
+}};
+
+//This template provides the execute functions for a store
+def template MacroExecute {{
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ {
+ panic("Tried to execute a macroop directly!\n");
+ return NoFault;
+ }
+}};
+
output header {{
class SparcMacroInst : public SparcStaticInst
@@ -60,7 +87,9 @@ output header {{
return microOps[microPC];
}
- %(BasicExecPanic)s
+ %(MacroExecute)s
+ %(MacroInitiateAcc)s
+ %(MacroCompleteAcc)s
};
class SparcMicroInst : public SparcStaticInst
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 038919bd1..58d616a7a 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -52,6 +52,16 @@ output header {{
{
return (regNum & (~1)) | ((regNum & 1) << 5);
}
+
+ static inline unsigned int dfprl(unsigned int regNum)
+ {
+ return dfpr(regNum) & (~0x1);
+ }
+
+ static inline unsigned int dfprh(unsigned int regNum)
+ {
+ return dfpr(regNum) | 0x1;
+ }
}};
def operands {{
@@ -79,21 +89,43 @@ def operands {{
# differently, they get different operands. The single precision versions
# have an s post pended to their name.
'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
- 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+ 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
# Each Frd_N refers to the Nth double precision register from Frd.
# Note that this adds twice N to the register number.
- 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
- 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
- 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
- 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
- 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
- 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
- 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
- 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+ #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+ 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
+ #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
+ 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
+ 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
+ #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
+ 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
+ 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
+ #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
+ 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
+ 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
+ #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
+ 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
+ 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
+ #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
+ 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
+ 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
+ #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
+ 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
+ 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
+ #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+ 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
+ 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
- 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+ #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+ 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
+ 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
- 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
+ #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
+ 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
+ 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
# Registers which are used explicitly in instructions
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index 6d89c273a..8c9afcdb5 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -65,12 +65,32 @@ namespace X86ISA
{
class X86Fault : public FaultBase
{
+ protected:
+ const char * name()
+ {
+ return "generic_x86_fault";
+ }
+
void invoke(ThreadContext * tc)
{
panic("X86 faults are not implemented!");
}
};
+ class UnimpInstFault : public FaultBase
+ {
+ public:
+ const char * name()
+ {
+ return "unimplemented_micro";
+ }
+
+ void invoke(ThreadContext * tc)
+ {
+ panic("Unimplemented instruction!");
+ }
+ };
+
static inline Fault genPageTableFault(Addr va)
{
panic("Page table fault not implemented in x86!\n");
diff --git a/src/arch/x86/isa/base.isa b/src/arch/x86/isa/base.isa
index cd166b306..eba24f709 100644
--- a/src/arch/x86/isa/base.isa
+++ b/src/arch/x86/isa/base.isa
@@ -58,6 +58,38 @@
// Base class for sparc instructions, and some support functions
//
+let {{
+ # This class will help make dealing with output a little less verbose
+ class OutputBlocks(object):
+ def __init__(self, header_output="",
+ decoder_output="",
+ decode_block="",
+ exec_output=""):
+ self.header_output = header_output
+ self.decoder_output = decoder_output
+ self.decode_block = decode_block
+ self.exec_output = exec_output
+
+ def append(self, blocks):
+ if isinstance(blocks, list) or isinstance(blocks, tuple):
+ assert(len(blocks) == 4)
+ self.header_output += blocks[0]
+ self.decoder_output += blocks[1]
+ self.decode_block += blocks[2]
+ self.exec_output += blocks[3]
+ else:
+ self.header_output += blocks.header_output
+ self.decoder_output += blocks.decoder_output
+ self.decode_block += blocks.decode_block
+ self.exec_output += blocks.exec_output
+
+ def makeList(self):
+ return (self.header_output,
+ self.decoder_output,
+ self.decode_block,
+ self.exec_output)
+}};
+
output header {{
/**
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index fed6dda28..4e044363b 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -61,11 +61,11 @@
0x1: decode OPCODE_OP_TOP5 {
format WarnUnimpl {
0x00: decode OPCODE_OP_BOTTOM3 {
- 0x4: Inst::add(rAl,Ib);
- 0x5: Inst::add(rAx,Iz);
+ 0x4: Inst::ADD(rAl,Ib);
+ 0x5: Inst::ADD(rAx,Iz);
0x6: push_ES();
0x7: pop_ES();
- default: MultiInst::add(OPCODE_OP_BOTTOM3,
+ default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
[Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]);
}
0x01: decode OPCODE_OP_BOTTOM3 {
@@ -123,12 +123,12 @@
0x7: das();
}
0x06: decode OPCODE_OP_BOTTOM3 {
- 0x4: Inst::xor(rAl,Ib);
- 0x5: Inst::xor(rAx,Iz);
+ 0x4: Inst::XOR(rAl,Ib);
+ 0x5: Inst::XOR(rAx,Iz);
0x6: M5InternalError::error(
{{"Tried to execute the SS segment override prefix!"}});
0x7: aaa();
- default: MultiInst::xor(OPCODE_OP_BOTTOM3,
+ default: MultiInst::XOR(OPCODE_OP_BOTTOM3,
[Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]);
}
0x07: decode OPCODE_OP_BOTTOM3 {
@@ -237,11 +237,11 @@
0x7: xchg_Ev_Gv();
}
0x11: decode OPCODE_OP_BOTTOM3 {
- 0x0: mov_Eb_Gb();
- 0x1: mov_Ev_Gv();
- 0x2: mov_Gb_Eb();
- 0x3: mov_Gv_Ev();
- 0x4: mov_MwRv_Sw();
+ 0x0: Inst::MOV(); //mov_Eb_Gb();
+ 0x1: Inst::MOV(); //mov_Ev_Gv();
+ 0x2: Inst::MOV(); //mov_Gb_Eb();
+ 0x3: Inst::MOV(); //mov_Gv_Ev();
+ 0x4: Inst::MOV(); //mov_MwRv_Sw();
0x5: lea_Gv_M();
0x6: mov_Sw_MwRv();
0x7: group10_Ev(); //Make sure this is Ev
diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa
index 7ad5ecd48..8f91c249c 100644
--- a/src/arch/x86/isa/formats/multi.isa
+++ b/src/arch/x86/isa/formats/multi.isa
@@ -72,7 +72,7 @@ def format Inst(*opTypeSet) {{
(header_output,
decoder_output,
decode_block,
- exec_output) = doInst(name, Name, list(opTypeSet))
+ exce_output) = doInst(name, Name, list(opTypeSet)).makeList()
}};
def format MultiInst(switchVal, *opTypeSets) {{
@@ -82,5 +82,5 @@ def format MultiInst(switchVal, *opTypeSets) {{
(header_output,
decoder_output,
decode_block,
- exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher)
+ exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher).makeList()
}};
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 7d41a2dea..663ec7aee 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -55,26 +55,30 @@
//
// Authors: Gabe Black
+//////////////////////////////////////////////////////////////////////////////
+//
+// Architecture independent
+//
+
// Execute method for macroops.
def template MacroExecPanic {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
panic("Tried to execute macroop directly!");
- M5_DUMMY_RETURN
+ return NoFault;
}
}};
output header {{
- // Base class for most macroops, except ones that need to commit as
- // they go.
- class X86MacroInst : public StaticInst
+ // Base class for macroops
+ class MacroOp : public StaticInst
{
protected:
const uint32_t numMicroOps;
//Constructor.
- X86MacroInst(const char *mnem, ExtMachInst _machInst,
+ MacroOp(const char *mnem, ExtMachInst _machInst,
uint32_t _numMicroOps)
: StaticInst(mnem, _machInst, No_OpClass),
numMicroOps(_numMicroOps)
@@ -84,7 +88,7 @@ output header {{
flags[IsMacroOp] = true;
}
- ~X86MacroInst()
+ ~MacroOp()
{
delete [] microOps;
}
@@ -97,10 +101,29 @@ output header {{
return microOps[microPC];
}
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return mnemonic;
+ }
+
%(MacroExecPanic)s
};
}};
+// Basic instruction class declaration template.
+def template MacroDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+ // Constructor.
+ %(class_name)s(ExtMachInst machInst);
+ };
+}};
+
// Basic instruction class constructor template.
def template MacroConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
@@ -113,23 +136,27 @@ def template MacroConstructor {{
}
}};
+//////////////////////////////////////////////////////////////////////////////
+//
+// X86 specific
+//
+
let {{
def genMacroOp(name, Name, opSeq):
- baseClass = 'X86MacroInst'
- numMicroOps = len(opSeq.ops)
+ numMicroOps = len(opSeq)
allocMicroOps = ''
micropc = 0
- for op in opSeq.ops:
+ for op in opSeq:
allocMicroOps += \
"microOps[%d] = %s;\n" % \
- (micropc, op.getAllocator(True, op.delayed,
+ (micropc, op.getAllocator('"' + name + '"', True, False, #op.delayed,
micropc == 0,
micropc == numMicroOps - 1))
micropc += 1
- iop = InstObjParams(name, Name, baseClass,
+ iop = InstObjParams(name, Name, 'MacroOp',
{'code' : '', 'num_micro_ops' : numMicroOps,
'alloc_micro_ops' : allocMicroOps})
- header_output = BasicDeclare.subst(iop)
+ header_output = MacroDeclare.subst(iop)
decoder_output = MacroConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = ''
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 23567aae9..9d21b6bcc 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -85,7 +85,7 @@ let {{
text += ", false"
return text
- def getAllocator(self, *microFlags):
+ def getAllocator(self, mnemonic, *microFlags):
args = ''
signature = "<"
emptySig = True
@@ -104,7 +104,7 @@ let {{
else:
raise Exception, "Unrecognized operand type."
signature += ">"
- return 'new %s%s(machInst%s%s)' % (self.className, signature, self.microFlagsText(microFlags), args)
+ return 'new %s%s(machInst, %s%s%s)' % (self.className, signature, mnemonic, self.microFlagsText(microFlags), args)
}};
let{{
@@ -123,7 +123,7 @@ let{{
# the beginning of the line, so the previous component is stripped
# before continuing.
labelRe = re.compile(r'^[ \t]*(?P<label>\w\w*)[ \t]:')
- lineRe = re.compile(r'^(?P<line>[^\n][^\n]*)$')
+ lineRe = re.compile(r'^(?P<line>..*)(\n|$)')
classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)')
# This recognizes three different flavors of operands:
# 1. Raw decimal numbers composed of digits between 0 and 9
@@ -145,14 +145,14 @@ let{{
# Get a line and seperate it from the rest of the code
line = lineMatch.group("line")
orig_line = line
- # print "Parsing line %s" % line
+ #print "Parsing line %s" % line
code = lineRe.sub('', code, 1)
# Find the label, if any
labelMatch = labelRe.search(line)
if labelMatch != None:
statement.label = labelMatch.group("label")
- # print "Found label %s." % statement.label
+ #print "Found label %s." % statement.label
# Clear the label from the statement
line = labelRe.sub('', line, 1)
@@ -163,7 +163,7 @@ let{{
% orig_line
else:
statement.className = classMatch.group("className")
- # print "Found class name %s." % statement.className
+ #print "Found class name %s." % statement.className
# Clear the class name from the statement
line = classRe.sub('', line, 1)
@@ -185,9 +185,9 @@ let{{
print "Problem parsing operand in statement: %s" \
% orig_line
line = opRe.sub('', line, 1)
- # print "Found operand %s." % statement.args[-1]
+ #print "Found operand %s." % statement.args[-1]
opMatch = opRe.search(line)
- # print "Found operands", statement.args
+ #print "Found operands", statement.args
# Add this statement to our collection
statements.append(statement)
@@ -215,11 +215,14 @@ let{{
arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1
micropc += 1
+ if len(statements) == 0:
+ raise Exception, "Didn't find any microops in microcode: \n%s" % orig_code
+
# If we can implement this instruction with exactly one microop, just
# use that directly.
if len(statements) == 1:
decode_block = "return %s;" % \
- statements[0].getAllocator()
+ statements[0].getAllocator('"' + name + '"')
return ('', '', decode_block, '')
else:
# Build a macroop to contain the sequence of microops we've
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index 4254994f3..f0aab7872 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -69,20 +69,33 @@ output header {{
class X86MicroOpBase : public X86StaticInst
{
protected:
+ const char * instMnem;
uint8_t opSize;
uint8_t addrSize;
- X86MicroOpBase(bool isMicro, bool isDelayed,
+ X86MicroOpBase(ExtMachInst _machInst,
+ const char *mnem, const char *_instMnem,
+ bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
- const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
- X86StaticInst(mnem, _machInst, __opClass)
+ X86StaticInst(mnem, _machInst, __opClass),
+ instMnem(_instMnem)
{
flags[IsMicroOp] = isMicro;
flags[IsDelayedCommit] = isDelayed;
flags[IsFirstMicroOp] = isFirst;
flags[IsLastMicroOp] = isLast;
}
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "\t%s.%s", instMnem, mnemonic);
+
+ return ss.str();
+ }
};
}};
@@ -127,7 +140,7 @@ let {{
}};
// A tmeplate for building a specialized version of the microcode
-// instruction which knows specifies which arguments it wants
+// instruction which specifies which arguments it wants
def template MicroOpDeclare {{
template<>
class %(class_name)s%(signature)s : public X86MicroOpBase
@@ -137,11 +150,15 @@ def template MicroOpDeclare {{
void buildMe();
public:
- %(class_name)s(bool isMicro, bool isDelayed,
- bool isFirst, bool isLast,
- ExtMachInst _machInst %(param_arg_dec)s);
+ %(class_name)s(ExtMachInst _machInst,
+ const char * instMnem,
+ bool isMicro, bool isDelayed,
+ bool isFirst, bool isLast
+ %(param_arg_dec)s);
- %(class_name)s(ExtMachInst _machInst %(param_arg_dec)s);
+ %(class_name)s(ExtMachInst _machInst,
+ const char * instMnem
+ %(param_arg_dec)s);
%(BasicExecDeclare)s
};
@@ -155,19 +172,21 @@ def template MicroOpConstructor {{
}
inline %(class_name)s%(signature)s::%(class_name)s(
- ExtMachInst machInst %(param_arg_dec)s) :
- %(base_class)s(false, false, false, false,
- "%(mnemonic)s", machInst, %(op_class)s)
+ ExtMachInst machInst, const char * instMnem
+ %(param_arg_dec)s) :
+ %(base_class)s(machInst, "%(mnemonic)s", instMnem,
+ false, false, false, false, %(op_class)s)
%(param_init)s
{
buildMe();
}
inline %(class_name)s%(signature)s::%(class_name)s(
- bool isMicro, bool isDelayed, bool isFirst, bool isLast,
- ExtMachInst machInst %(param_arg_dec)s)
- : %(base_class)s(isMicro, isDelayed, isFirst, isLast,
- "%(mnemonic)s", machInst, %(op_class)s)
+ ExtMachInst machInst, const char * instMnem,
+ bool isMicro, bool isDelayed, bool isFirst, bool isLast
+ %(param_arg_dec)s)
+ : %(base_class)s(machInst, "%(mnemonic)s", instMnem,
+ isMicro, isDelayed, isFirst, isLast, %(op_class)s)
%(param_init)s
{
buildMe();
diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa
index bb136fc81..d877152eb 100644
--- a/src/arch/x86/isa/microops/microops.isa
+++ b/src/arch/x86/isa/microops/microops.isa
@@ -56,5 +56,8 @@
//Common microop stuff
##include "base.isa"
+//A microop that generates a specified fault
+##include "fault.isa"
+
//Integer microop definitions
##include "int.isa"
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 9cac09770..ff92c3551 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -67,30 +67,18 @@ let {{
# builder is called on the exploded contents of "vals" values to generate
# whatever code should be used.
def doSplitDecode(name, Name, builder, switchVal, vals, default = None):
- header_output = ''
- decoder_output = ''
- decode_block = 'switch(%s) {\n' % switchVal
- exec_output = ''
+ blocks = OutputBlocks()
+ blocks.decode_block += 'switch(%s) {\n' % switchVal
for (val, todo) in vals.items():
- (new_header_output,
- new_decoder_output,
- new_decode_block,
- new_exec_output) = builder(name, Name, *todo)
- header_output += new_header_output
- decoder_output += new_decoder_output
- decode_block += '\tcase %s: %s\n' % (val, new_decode_block)
- exec_output += new_exec_output
+ built = builder(name, Name, *todo)
+ built.decode_block = '\tcase %s: %s\n' % (val, built.decode_block)
+ blocks.append(built)
if default:
- (new_header_output,
- new_decoder_output,
- new_decode_block,
- new_exec_output) = builder(name, Name, *default)
- header_output += new_header_output
- decoder_output += new_decoder_output
- decode_block += '\tdefault: %s\n' % new_decode_block
- exec_output += new_exec_output
- decode_block += '}\n'
- return (header_output, decoder_output, decode_block, exec_output)
+ built = builder(name, Name, *default)
+ built.decode_block = '\tdefault: %s\n' % built.decode_block
+ blocks.append(built)
+ blocks.decode_block += '}\n'
+ return blocks
}};
let {{
@@ -143,6 +131,7 @@ let {{
# This needs to refer to memory, but we'll fill in the details
# later. It needs to take into account unaligned memory
# addresses.
+ code = "GenFault ${new UnimpInstFault}\n" + code
memCode = opRe.sub("%0", code)
memTypes = copy.copy(opTypes)
memTypes.pop(-1)
@@ -156,6 +145,7 @@ let {{
# This needs to refer to memory, but we'll fill in the details
# later. It needs to take into account unaligned memory
# addresses.
+ code = "GenFault ${new UnimpInstFault}\n" + code
code = opRe.sub("%0", code)
elif opType.tag in ("PR", "R", "VR"):
# There should probably be a check here to verify that mod
@@ -168,5 +158,7 @@ let {{
# At this point, we've built up "code" to have all the necessary extra
# instructions needed to implement whatever types of operands were
# specified. Now we'll assemble it it into a StaticInst.
- return assembleMicro(name, Name, code)
+ blocks = OutputBlocks()
+ blocks.append(assembleMicro(name, Name, code))
+ return blocks
}};
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-23 19:39:20 +0000