7 files changed, 16 insertions, 0 deletions

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 2eefead16..e1f50ddc2 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -40,6 +40,9 @@ namespace AlphaISA {
 using AlphaISAInst::MaxInstSrcRegs;
 using AlphaISAInst::MaxInstDestRegs;
 
+// Locked read/write flags are can't be detected by the ISA parser
+const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
+
 typedef uint8_t RegIndex;
 typedef uint64_t IntReg;
 
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 1a688af56..cd2f1f9b8 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -55,6 +55,7 @@ namespace ArmISA {
 const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
     ArmISAInst::MaxInstSrcRegs;
 using ArmISAInst::MaxInstDestRegs;
+using ArmISAInst::MaxMiscDestRegs;
 
 typedef uint16_t  RegIndex;
 
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 1b0d46410..60e7e226b 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -726,6 +726,7 @@ class OperandList(object):
         self.numDestRegs = 0
         self.numFPDestRegs = 0
         self.numIntDestRegs = 0
+        self.numMiscDestRegs = 0
         self.memOperand = None
         for op_desc in self.items:
             if op_desc.isReg():
@@ -739,6 +740,8 @@ class OperandList(object):
                         self.numFPDestRegs += 1
                     elif op_desc.isIntReg():
                         self.numIntDestRegs += 1
+                    elif op_desc.isControlReg():
+                        self.numMiscDestRegs += 1
             elif op_desc.isMem():
                 if self.memOperand:
                     error("Code block has more than one memory operand.")
@@ -747,6 +750,8 @@ class OperandList(object):
             parser.maxInstSrcRegs = self.numSrcRegs
         if parser.maxInstDestRegs < self.numDestRegs:
             parser.maxInstDestRegs = self.numDestRegs
+        if parser.maxMiscDestRegs < self.numMiscDestRegs:
+            parser.maxMiscDestRegs = self.numMiscDestRegs
         # now make a final pass to finalize op_desc fields that may depend
         # on the register enumeration
         for op_desc in self.items:
@@ -1001,6 +1006,7 @@ namespace %(namespace)s {
 
     const int MaxInstSrcRegs = %(MaxInstSrcRegs)d;
     const int MaxInstDestRegs = %(MaxInstDestRegs)d;
+    const int MaxMiscDestRegs = %(MaxMiscDestRegs)d;
 
 } // namespace %(namespace)s
 
@@ -1036,6 +1042,7 @@ class ISAParser(Grammar):
 
         self.maxInstSrcRegs = 0
         self.maxInstDestRegs = 0
+        self.maxMiscDestRegs = 0
 
     #####################################################################
     #
@@ -1990,6 +1997,7 @@ StaticInstPtr
         # value of the globals.
         MaxInstSrcRegs = self.maxInstSrcRegs
         MaxInstDestRegs = self.maxInstDestRegs
+        MaxMiscDestRegs = self.maxMiscDestRegs
         # max_inst_regs.hh
         self.update_if_needed('max_inst_regs.hh',
                               max_inst_regs_template % vars())
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 0e5cbfc91..807fd825f 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -43,6 +43,7 @@ namespace MipsISA
 
 using MipsISAInst::MaxInstSrcRegs;
 using MipsISAInst::MaxInstDestRegs;
+using MipsISAInst::MaxMiscDestRegs;
 
 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 0d32201c2..2d09677b2 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -38,6 +38,7 @@ namespace PowerISA {
 
 using PowerISAInst::MaxInstSrcRegs;
 using PowerISAInst::MaxInstDestRegs;
+using PowerISAInst::MaxMiscDestRegs;
 
 typedef uint8_t RegIndex;
 
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 91904f42b..8c61a070c 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -42,6 +42,7 @@ namespace SparcISA
 
 using SparcISAInst::MaxInstSrcRegs;
 using SparcISAInst::MaxInstDestRegs;
+using SparcISAInst::MaxMiscDestRegs;
 
 typedef uint64_t IntReg;
 typedef uint64_t MiscReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 66f5dab80..20385a960 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -49,6 +49,7 @@ namespace X86ISA
 {
 using X86ISAInst::MaxInstSrcRegs;
 using X86ISAInst::MaxInstDestRegs;
+using X86ISAInst::MaxMiscDestRegs;
 const int NumMiscArchRegs = NUM_MISCREGS;
 const int NumMiscRegs = NUM_MISCREGS;