3 files changed, 33 insertions, 18 deletions

diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 962d4609f..67f6c98e4 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -89,12 +89,26 @@ namespace AlphaISA
     MiscReg
     MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
     {
+        switch(misc_reg) {
+          case MISCREG_FPCR:
+            return fpcr;
+          case MISCREG_UNIQ:
+            return uniq;
+          case MISCREG_LOCKFLAG:
+            return lock_flag;
+          case MISCREG_LOCKADDR:
+            return lock_addr;
+          case MISCREG_INTR:
+            return intr_flag;
 #if FULL_SYSTEM
-        return readIpr(misc_reg, tc);
+          default:
+            return readIpr(misc_reg, tc);
 #else
-        panic("No faulting misc regs in SE mode!");
-        return 0;
+          default:
+            panic("No faulting misc regs in SE mode!");
+            return 0;
 #endif
+        }
     }
 
     void
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 2086473d6..59eb18c9c 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1180,15 +1180,16 @@ class IntRegOperand(Operand):
         if (self.ctype == 'float' or self.ctype == 'double'):
             error(0, 'Attempt to read integer register as FP')
         if (self.size == self.dflt_size):
-            return '%s = xc->readIntReg(this, %d);\n' % \
+            return '%s = xc->readIntRegOperand(this, %d);\n' % \
                    (self.base_name, self.src_reg_idx)
         elif (self.size > self.dflt_size):
-            int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx)
+            int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
+                          (self.src_reg_idx)
             if (self.is_signed):
                 int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
             return '%s = %s;\n' % (self.base_name, int_reg_val)
         else:
-            return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
+            return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
                    (self.base_name, self.src_reg_idx, self.size-1)
 
     def makeWrite(self):
@@ -1201,7 +1202,7 @@ class IntRegOperand(Operand):
         wb = '''
         {
             %s final_val = %s;
-            xc->setIntReg(this, %d, final_val);\n
+            xc->setIntRegOperand(this, %d, final_val);\n
             if (traceData) { traceData->setData(final_val); }
         }''' % (self.dflt_ctype, final_val, self.dest_reg_idx)
         return wb
@@ -1227,13 +1228,13 @@ class FloatRegOperand(Operand):
         bit_select = 0
         width = 0;
         if (self.ctype == 'float'):
-            func = 'readFloatReg'
+            func = 'readFloatRegOperand'
             width = 32;
         elif (self.ctype == 'double'):
-            func = 'readFloatReg'
+            func = 'readFloatRegOperand'
             width = 64;
         else:
-            func = 'readFloatRegBits'
+            func = 'readFloatRegOperandBits'
             if (self.ctype == 'uint32_t'):
                 width = 32;
             elif (self.ctype == 'uint64_t'):
@@ -1259,18 +1260,18 @@ class FloatRegOperand(Operand):
         width = 0
         if (self.ctype == 'float'):
             width = 32
-            func = 'setFloatReg'
+            func = 'setFloatRegOperand'
         elif (self.ctype == 'double'):
             width = 64
-            func = 'setFloatReg'
+            func = 'setFloatRegOperand'
         elif (self.ctype == 'uint32_t'):
-            func = 'setFloatRegBits'
+            func = 'setFloatRegOperandBits'
             width = 32
         elif (self.ctype == 'uint64_t'):
-            func = 'setFloatRegBits'
+            func = 'setFloatRegOperandBits'
             width = 64
         else:
-            func = 'setFloatRegBits'
+            func = 'setFloatRegOperandBits'
             final_ctype = 'uint%d_t' % self.dflt_size
             if (self.size != self.dflt_size and self.is_signed):
                 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index cdb892b3f..153f3f949 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -99,7 +99,7 @@ output exec {{
             int size = sizeof(src_op) * 8;
 
             for (int i = 0; i < inst->numSrcRegs(); i++) {
-                uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
+                uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
 
                 if (isNan(&src_bits, size) ) {
                     if (isSnan(&src_bits, size)) {
@@ -113,7 +113,7 @@ output exec {{
                         mips_nan = src_bits;
                     }
 
-                    xc->setFloatRegBits(inst, 0, mips_nan, size);
+                    xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
                     if (traceData) { traceData->setData(mips_nan); }
                     return true;
                 }
@@ -139,7 +139,7 @@ output exec {{
                 }
 
                 //Set value to QNAN
-                cpu->setFloatRegBits(inst, 0, mips_nan, size);
+                cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
 
                 //Read FCSR from FloatRegFile
                 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);