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-rw-r--r--src/arch/arm/isa.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 5d34e188a..f6677323e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1476,7 +1476,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
val, newVal);
} else {
- ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
+ ArmFault *armFault = static_cast<ArmFault *>(fault.get());
// Set fault bit and FSR
FSR fsr = armFault->getFsr(tc);
@@ -1725,7 +1725,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
"MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
val, newVal);
} else {
- ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
+ ArmFault *armFault = static_cast<ArmFault *>(fault.get());
// Set fault bit and FSR
FSR fsr = armFault->getFsr(tc);